Datasheet

Multipurpose Register

The Multipurpose Register (MPR) function, MPR access mode, is used to write/read specialized data to/from

the DRAM. The MPR consists of four logical pages, MPR Page 0 through MPR Page 3, with each page having

four 8-bit registers, MPR0 through MPR3.

MPR mode enable and page selection is done with MRS commands. Data bus inversion (DBI) is not allowed

during MPR Read operation. Prior to issuing the MRS command, all banks must be in the idle state (all banks

precharged and t

met). After MPR is enabled, any subsequent RD or RDA commands will be redirected to a

specific mode register.

Once the MPR access mode is enabled (MR3 A[2] = 1), only the following commands are allowed: MRS,

RD, RDA WR, WRA, DES, REF, and Reset; RDA/WRA have the same functionality as RD/WR which means

the auto precharge part of RDA/WRA is ignored. The mode register location is specified with the Read command

using address bits. The MR is split into upper and lower halves to align with a burst length limitation of 8. Power-

down mode and Self Refresh command are not allowed during MPR enable mode.

No other command can be issued within t

RFC

after a REF command has been issued; 1x refresh (only) is to be

used during MPR access mode. While in MPR access mode, MPR read or write sequences must be completed

prior to a Refresh command.

MR3 Setting for the MPR Access Mode

Mode register MR3 controls the Multi-Purpose Registers (MPR) used for training. MR3 is written by asserting

CS#, RAS#/A16, CAS#/A15 and WE#/A14 low, ACT#, BA0 and BA1 high and BG0 low while controlling the states

of the address pins, Refer to the MR3 definition table for more detail.

Table 29. DRAM Address to MPR UI Translation

MPR Location

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

DRAM address – Ax

MPR UI – UIx

UI0

UI1

UI2

UI3

UI4

UI5

UI6

UI7

AS4C256M16D4

Confidential

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Rev.1.0 Aug.2019