Datasheet
Ta0 Ta1 Tb0 Tb1 Tc0 Tc1 Tc2 Td0 Td1T0 Te0
t
PAR_UNKNOWN
DON'T CARETIME BREAK
DES
SRX
1
DES VALID
CK#
CK
NOTE 1. SelfRefresh Abort = Disable: MR4 [A9=0]
NOTE 2 Input commands are bounded by tXSDLL, tXS, tXS_ABORT and tXS_FAST timing.
NOTE 3 Command execution is unknown the corresponding DRAM internal state change may or may not occur. The DRAM Controller should consider
both cases and make sure that the command sequence meets the specifications.
NOTE 4 Normal operation with parity latency(CA Parity Persistent Error Mode disabled). Parity checking off until Parity Error Status bit cleared.
NOTE 5 Only MRS (limited to those described in the Self-Refresh Operation section), ZQCS or ZQCL command allowed.
NOTE 6 Valid commands not requiring a locked DLL
NOTE 7 Valid commands requiring a locked DLL
NOTE 8 This figure shows the case from which the error occurred after tXS FAST_An error also occur after tXS_ABORT and tXS.
t
PAR_ALERT_PW
t
RP
t
PAR_ALERT_ON
DES
(1,5)
DES
6
Command execution unknown
ERROR
2
DES
1
Command not executed
VALID
3
Command executed
t≧
2nCK
VALID
Tf0
t
IS
CKE
CMD/
ADDR
ALERT#
DES
REF
5
ERROR
VALID
2
VALID
2
VALID
2
DES
REF
2
DES
REF
2,3
VALID
t
XS_FAST
8
t
XS
t
XSDLL
2,4,5
2,4,6 2,4,7
Figure 59. CA Parity Error Checking - SRX
Command/Address parity entry and exit timings
When in CA Parity mode, including entering and exiting CA Parity mode, users must wait t
MRD_PAR
before
issuing another MRS command, and wait t
MOD_PAR
before any other commands.
t
MOD_PAR
= t
MOD
+ PL
t
MRD_PAR
= t
MOD
+ PL
For CA parity entry, PL in the equations above is the parity latency programmed with the MRS command
entering CA parity mode.
For CA parity exit, PL in the equations above is the programmed parity latency prior to the MRS command
exiting CA parity mode.
Ta1 Ta2 Tb0 Tb1 Tb2Ta0
t
MRD_PAR
MRSDES DES DES MRS DES
PL = 0
CK#
CK
CMD
Settings
Updating Setting PL = N
NOTE 1. tMRD_PAR = tMOD + N; where N is the programmed parity latency with the MRS command
entering CA parity mode.
NOTE 2. Parity check is not available at Ta1 of MRS command due to PL=0 being valid.
NOTE 3. In case parity error happens at Tb1 of MRS command, tPAR_ALERT_ON is ‘N[nCK] + 6[ns]’.
Enable Parity change
PL from 0 to N
Figure 60. Parity entry timing example - t
MRD_PAR
AS4C256M16D4
Confidential
- 70 of 201 -
Rev.1.0 Aug.2019