Datasheet

A12/BC#
Input
Burst Chop: A12/BC# is sampled during Read and Write commands to determine if
burst chop (on-the-fly) will be performed. (high, no burst chop; low: burst chopped).
See command truth table for details.
Reset#
Input
Active Low Asynchronous Reset: Reset is active when Reset# is low, and inactive
when Reset# is high. Reset# must be high during normal operation. Reset# is a
CMOS rail-to-rail signal with DC high and low at 80% and 20% of V
DD
.
DQ0-DQ15
Input /
Output
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register
then CRC code is added at the end of Data Burst. Any DQ from DQ0~DQ3 may
indicate the internal V
REF
level during test via Mode Register Setting MR4 A4=high.
During this mode, R
TT
should be set Hi-Z.
LDQS,
LDQS#,
UDQS,
UDQS#,
Input /
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read
data, centered in write data. LDQS corresponds to the data on DQ0-DQ7; UDQS
corresponds to the data on DQ8-DQ15. The data strobe LDQS and UDQS are
paired with differential signals LDQS#, and UDQS#, respectively, to provide
differential pair signaling to the system during reads and writes. DDR4 SDRAM
supports differential data strobe only and does not support single-ended.
PAR
Input
Command and Address Parity Input: DDR4 Supports Even Parity check in DRAM
with MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity
with ACT#, RAS#/A16, CAS#/A15, WE#/A14, BG0, BA0-BA1, and A16-A0. Command
and address inputs shall have parity check performed when commands are latched
via the rising edge of CK and when CS# is low.
Alert#
Input /
Output
Alert: It has multi functions such as CRC error flag, Command and Address Parity
error flag as Output signal. If there is error in CRC, then Alert# goes low for the
period time interval and goes back high. If there is error in Command Address Parity
Check, then Alert# goes low for relatively long period until ongoing DRAM internal
recovery transaction to complete. During Connectivity Test mode, this pin works as
input. Using this signal or not is dependent on system. In case of not connected as
Signal, Alert# Pin must be bounded to V
DD
on board.
TEN
Input
Connectivity Test Mode Enable: Connectivity Test Mode is active when TEN is
high, and inactive when TEN is low. TEN must be low during normal operation. TEN
is a CMOS rail-to-rail signal with AC high and low at 80% and 20% of V
DD
(960mV
for DC high and 240mV for DC low). Using this signal or not is dependent on
System. This pin may be DRAM internally pulled low through a weak pull-down
resistor to V
SS
.
NC
-
No Connect: These pins should be left unconnected.
V
DD
Supply
Power Supply: +1.2V 0.06V.
V
SS
Supply
Ground
V
DDQ
Supply
DQ Power Supply: +1.2V 0.06V.
V
SSQ
Supply
DQ Ground
V
PP
Supply
DRAM Activating Power Supply: 2.5V ( 2.375V min , 2.75V max)
V
REFCA
Supply
Reference voltage for CA
ZQ
Supply
Reference pin for ZQ calibration.
NOTE: Input only pins (BG0, BA0-BA1, A0-A16, ACT#, RAS#/A16, CAS#/A15, WE#/A14, CS#, CKE, ODT, and RESET#) do not supply termination.
AS4C256M16D4
Confidential
- 7 of 201 -
Rev.1.0 Aug.2019