Datasheet
Table 28. Mode Registers for C/A Parity
C/A Parity Latency
MR5[2:0]*
Speed bins
C/A Parity Error Status
MR5[4]
Errant C/A Frame
000 = Disabled
-
0 = Clear
ACT#, BG0, BA0, BA1, PAR,
A16/RAS#, A15/CAS#,
A14/WE#, A13:A0
001= 4 Clocks
1600,1866,2133
010= 5 Clocks
2400,2666
1 = Error
011= 6 Clocks
RFU
100= 8 Clocks
RFU
Note 1. Parity Latency is applied to all commands.
Note 2. Parity Latency can be changed only from a C/A Parity disabled state, i.e. a direct change from PL= 4 → PL= 5 is not allowed.
Correct sequence is PL= 4 → Disabled → PL= 5.
Note 3. Parity Latency is applied to write and read latency. Write Latency = AL+CWL+PL. Read Latency = AL+CL+PL.
T1 Ta0 Ta1 Ta2 Tb0 Tc0 Tc1 Td0 Te0T0 Te1
t
PAR_UNKNOWN
2
DON'T CARETIME BREAK
VALID
2
VALID
2
VALID
2
ERROR
VALID VALID VALID
DES
REF
2
DES
REF
2
VALID
3
CK#
CK
NOTE 1. DRAM is emptying queues, Precharge All and parity checking off until Parity Error Status bit cleared.
NOTE 2. Command execution is unknown the corresponding DRAM internal state change may or may not occur. The DRAM Controller
should consider both cases and make sure that the command sequence meets the specifications.
NOTE 3. Normal operation with parity latency(CA Parity Persistent Error Mode disabled). Parity checking off until Parity Error Status bit cleared.
CMD/
ADDR
t
PAR_ALERT_PW
1
t
RP
t
PAR_ALERT_ON
ALERT#
VALID
3
VALID
2
DES
REF
2
Command execution unknown
ERROR
VALID
Command not executed
VALID
3
Command executed
Figure 55. Normal CA Parity Error Checking Operation
T1 Ta0 Ta1 Ta2 Tb0 Tc0 Tc1 Td0 Te0T0 Te1
t
PAR_UNKNOWN
2
DON'T CARETIME BREAK
VALID
2
VALID
2
VALID
2
ERROR
VALID VALID VALID DES DES VALID
3
CK#
CK
NOTE 1. DRAM is emptying queues, Precharge All and parity check re-enable finished by tPAR_ALERT_PW.
NOTE 2. Command execution is unknown the corresponding DRAM internal state change may or may not occur. The DRAM Controller should
consider both cases and make sure that the command sequence meets the specifications.
NOTE 3. Normal operation with parity latency and parity checking (CA Parity Persistent Error Mode enabled).
CMD/
ADDR
t
PAR_ALERT_PW
1
t
RP
t
PAR_ALERT_ON
ALERT#
DES
VALID
2
DES
Command execution unknown
ERROR
VALID
Command not executed
VALID
3
Command executed
t≧2nCKt
PAR_ALERT_RSP
Figure 56. Persistent CA Parity Error Checking Operation
AS4C256M16D4
Confidential
- 68 of 201 -
Rev.1.0 Aug.2019