Datasheet

Command Address Parity (CA Parity)
[A2:A0] of MR5 are defined to enable or disable C/A Parity in the DRAM. The default state of the C/A Parity
bits is disabled. If C/A parity is enabled by programming a non-zero value to C/A Parity Latency in the mode
register (the Parity Error bit must be set to zero when enabling C/A any Parity mode), then the DRAM has to
ensure that there is no parity error before executing the command. The additional delay for executing the
commands versus a parity disabled mode is programmed in the mode register (MR5, A2:A0) when C/A Parity
is enabled (PL: Parity Latency) and is applied to commands that are latched via the rising edge of CK when
CS# is low. The command is held for the time of the Parity Latency before it is executed inside the device.
This means that issuing timing of internal command is determined with PL. When C/A Parity is enabled,
only DES is allowed between valid commands to prevent DRAM from any malfunctioning. CA Parity Mode is
supported when DLL-on Mode is enabled, use of CA Parity Mode when DLL-off Mode is enabled is not allowed.
C/A Parity signal (PAR) covers ACT#, RAS#/A16, CAS#/A15, WE#/A14 and the address bus including bank
address and bank group bits. The control signals CKE, ODT and CS# are not included. (e.g., for a 4 Gbit x8
monolithic device, parity is computed across BG0, BA1, BA0, A16/RAS#, A15/CAS#, A14/WE#, A13-A0 and
ACT#). (The DRAM treats any unused address pins internally as zeros; for example, if a common die has
stacked pins but the device is used in a monolithic application, then the address pins used for stacking and
not connected are treated internally as zeros.)
The convention of parity is even parity i.e. valid parity is defined as an even number of ones across the
inputs used for parity computation combined with the parity signal. In other words the parity bit is chosen so
that the total number of 1’s in the transmitted signal, including the parity bit is even.
If a DRAM detects a C/A parity error in any command as qualified by CS# then it must perform the following
steps:
- Ignore the erroneous command. Commands in max NnCK window (tPAR_UNKNOWN) prior to the erroneous
command are not guaranteed to be executed. When a Read command in this NnCK window is not
executed, the DRAM does not activate DQS outputs.
- Log the error by storing the erroneous command and address bits in the error log.
- Set the Parity Error Status bit in the mode register to 1. The Parity Error Status bit must be set before the
ALERT# signal is released by the DRAM (i.e. tPAR_ALERT_ON + tPAR_ALERT_PW(min)).
- Assert the ALERT# signal to the host (ALERT# is active low) within tPAR_ALERT_ON time.
- Wait for all in-progress commands to complete. These commands were received tPAR_UNKOWN before the
erroneous command. If a parity error occurs on a command issued between the tXS_Fast and tXS window
after self-refresh exit then the DRAM may delay the de-assertion of ALERT# signal as a result of any
internal on going refresh.
- Wait for tRAS_min before closing all the open pages. The DRAM is not executing any commands during the
window defined by (tPAR_ALERT_ON + tPAR_ALERT_PW).
- After tPAR_ALERT_PW_min has been satisfied, the DRAM may de-assert ALERT#.
- After the device has returned to a known pre-charged state it may de-assert ALERT#.
- After (tPAR_ALERT_ON + tPAR_ALERT_PW), the device is ready to accept commands for normal operation. Parity
latency will be in effect, however, parity checking will not resume until the memory controller has cleared the
Parity Error Status bit by writing a zero. (The DRAM will execute any erroneous commands until the bit is
cleared).
- It is possible that the device might have ignored a refresh command during the (tPAR_ALERT_ON + tPAR_ALERT_PW)
window or the refresh command is the first erroneous frame so it is recommended that the controller issues
extra refresh cycles as needed.
- The Parity Error Status bit may be read any time after (tPAR_ALERT_ON + tPAR_ALERT_PW) to determine which
DRAM had the error. The device maintains the Error Log for the first erroneous command until the Parity
Error Status bit is reset to zero.
Mode Register for C/A Parity Error is defined as follows. C/A Parity Latency bits are write only, Parity Error
Status bit is read/write and error logs are read only bits. The device controller can only program the Parity
Error Status bit to zero. If the DRAM controller illegally attempts to write a ‘1’ to the Parity Error Status bit the
DRAM does not guarantee that parity will be checked. The DRAM may opt to block the controller from writing
a ‘1’ to the Parity Error Status bit.
DDR4 SDRAM supports MR bit for Persistent Parity Error Mode. This mode is enabled by setting MR5 A[9]
= 1 and when it is enabled, DRAM resumes checking CA Parity after the ALERT# is deasserted, even if Parity
Error Status bit is set as High. If multiple errors occur before the Error Status bit is cleared the error log in MPR
page 1 should be treated as ‘Don’t Care’. In Persistent Parity Error Mode the ALERT# pulse will be asserted
and deasserted by the DRAM as defined with the min. and max. value for tPAR_ALERT_PW. The controller must
issue Deselect commands once it detects the ALERT# signal, this response time is defined as t
PAR_ALERT_RSP
.
The following figure captures the flow of events on the C/A bus and the ALERT# signal.
AS4C256M16D4
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Rev.1.0 Aug.2019