Datasheet

MRS
VALID
CK#
CK
ODT
RTT
NOTE:
RTT_PARK = Enable, RTT_NOM = Enable, Write Preamble Set = 2tCK and DLL = ON, CA parity is used.
AL + CWL + PL
DODTLOn = WL - 3
DQS, DQS#
DODTLoff = WL - 3
RTT_NOM RTT_PARK
tMOD_PDA
tPDA_S
tPDA_H
MR3 A4 = 0
(PDA Disable)
RTT_PARK
DQ0
(selected device)
Figure 53. MRS w/ per DRAM addressability (PDA) Exit
MRS MRS
MRS
CK#
CK
NOTE: CA parity is used..
AL + CWL + PL
DQS, DQS#
tMOD
tMRD_PDA
tPDA_S
tPDA_H
DQ0
(selected device)
MR3 A4 = 1
(PDA Enable)
Figure 54. PDA using Burst Chop 4
Since PDA mode may be used to program optimal V
REF
for the DRAM, the DRAM may incorrectly read DQ
level at the first DQS edge and the last falling DQS edge. It is recommended that DRAM samples DQ0 on
either the first falling or second rising DQS edges.
This will enable a common implementation between BC4 and BL8 modes on the DRAM. Controller is
required to drive DQ0 to a ‘Stable Low or High’ during the length of the data transfer for BC4 and BL8 cases.
AS4C256M16D4
Confidential
- 66 of 201 -
Rev.1.0 Aug.2019