Datasheet

Per DRAM Addressability
DDR4 allows programmability of a given device on a rank. As an example, this feature can be used to
program different ODT or V
REF
values on DRAM devices on a given rank.
1. Before entering ‘per DRAM addressability (PDA)’ mode, the write leveling is required.
 BL8 or BC4 may be used.
2. Before entering ‘per DRAM addressability (PDA)’ mode, the following Mode Register setting is possible.
 R
TT_PARK
MR5 A[8:6] = Enable
 R
TT_NOM
MR1 A[10:8] = Enable
3. Enable ‘per DRAM addressability (PDA)’ mode using MR3 A[4] = 1.
4. In the ‘per DRAM addressability’ mode, all MRS command is qualified with DQ0. The device captures DQ0
by using DQS signals. If the value on DQ0 is low, the DRAM executes the MRS command. If the value on
DQ0 is high, the DRAM ignores the MRS command. The controller can choose to drive all the DQ bits.
5. Program the desired devices and mode registers using MRS command and DQ0.
6. In the ‘per DRAM addressability’ mode, only MRS commands are allowed.
7. The mode register set command cycle time at PDA mode, AL + CWL + BL/2 - 0.5t
CK
+ t
MRD_PDA
+ (PL) is
required to complete the write operation to the mode register and is the minimum time required between
two MRS commands.
8. Remove the device from ‘per DRAM addressability’ mode by setting MR3 A[4] = 0. (This command will
require DQ0 = 0)
Note: Removing a device from per DRAM addressability mode will require programming the entire MR3 when
the MRS command is issued. This may impact some PDA values programmed within a rank as the exit
command is sent to the rank. In order to avoid such a case the PDA Enable/Disable Control bit is located in a
mode register that does not have any ‘per DRAM addressability’ mode controls.
In per DRAM addressability mode, device captures DQ0 using DQS signals the same as in a normal write
operation; However, Dynamic ODT is not supported. Extra care required for the ODT setting. If R
TT_NOM
MR1
A[10:8] = Enable, device data termination need to be controlled by ODT pin and apply the same timing
parameters (defined below). V
REFDQ
value must be set to either its midpoint or V
cent_DQ
(midpoint) in order to
capture DQ0 low level for entering PDA mode.
Table 27. Applied ODT Timing Parameter to PDA Mode
Symbol
Parameter
DODTLon
Direct ODT turn on latency
DODTLoff
Direct ODT turn off latency
t
ADC
R
TT
change timing skew
t
AONAS
Asynchronous R
TT_NOM
turn-on delay
t
AOFAS
Asynchronous R
TT_NOM
turn-off delay
MRS MRS
MRS
CK#
CK
ODT
RTT
NOTE:
RTT_PARK = Enable, RTT_NOM = Enable, Write Preamble Set = 2tCK and DLL = ON, CA parity is used.
AL + CWL + PL
DODTLOn = WL - 3
DQS, DQS#
DODTLoff = WL - 3
RTT_PARK RTT_NOM RTT_PARK
tMOD
tMRD_PDA
tPDA_S
tPDA_H
MR3 A4 = 1
(PDA Enable)
CMD
DQ0
(seeted device)
Figure 52. MRS w/ per DRAM addressability (PDA) issuing before MRS
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