Datasheet

The VREF increment/decrement step times are defined by VREF_time. The VREF_time is defined from t0 to t1,
where t1 is referenced to when the VREF voltage is at the final DC level within the VREF valid tolerance
(VREF_val_tol).
The VREF valid level is defined by VREF_val tolerance to qualify the step time t1. This parameter is used to
insure an adequate RC time constant behavior of the voltage level change after any Vref increment/decrement
adjustment. This parameter is only applicable for DRAM component level validation/characterization.
VREF_time is the time including up to VREFmin to VREFmax or VREFmax to VREFmin change in VREF voltage.
t0 - is referenced to MRS command clock
t1 - is referenced to the VREF_val_tol
MRS
CK#
CK
CMD
VREF Setting
Adjustment
VREF_time
Old VREF
Setting
Updating VREF Setting
New VREF
Setting
t0 t1
DQ
VREF
Figure 46. V
REF_time
timing diagram
VREFDQ Calibration Mode is entered via MRS command setting MR6 A[7] to 1 (0 disables VREFDQ Calibration
Mode), and setting MR6 A[6] to either 0 or 1 to select the desired range, and MR6 A[5:0] with a “don’t care”
setting (there is no default initial setting; whether VREFDQ training value (MR6 A[5:0]) at training mode entry
with MR6 A[7] = 1 is captured by the DRAM or not is vendor specific). The next subsequent MR command is
used to set the desired VREFDQ values at MR6 A[5:0]. Once VREFDQ Calibration Mode has been entered, VREFDQ
Calibration Mode legal commands may be issued once tVREFDQE has been satisfied. VREFDQ Calibration Mode
legal commands are ACT, WR, WRA, RD, RDA, PRE, DES, MRS to set VREFDQ values, and MRS to exit VREFDQ
Calibration Mode. Once VREFDQ Calibration Mode has been entered, “dummy” write commands may be issued
prior to adjusting VREFDQ value the first time VREFDQ calibration is performed after initialization. The “dummy”
write commands may have bubbles between write commands provided other DRAM timings are satisfied. A
possible example command sequence would be: WR1, DES, DES, DES, WR2, DES, DES, DES, WR3, DES,
DES, DES, WR4, DES, DES…….DES, DES, WR50, DES, DES, DES. Setting VREFDQ values requires MR6 [7]
set to 1, MR6 [6] unchanged from initial range selection, and MR6 A[5:0] set to desired VREFDQ value; if MR6
[7] is set to 0, MR6 [6:0] are not written. VREF_time must be satisfied after each MR6 command to set VREFDQ
value before the internal VREFDQ value is valid.
If PDA mode is used in conjunction with VREFDQ calibration, the PDA mode requirement that only MRS commands
are allowed while PDA mode is enabled is not waived. That is, the only VREFDQ Calibration Mode legal commands
noted above that may be used are the MRS commands, i.e. MRS to set VREFDQ values, and MRS to exit VREFDQ
Calibration Mode.
The last A [6:0] setting written to MR6 prior to exiting VREFDQ Calibration Mode is the range and value used
for the internal VREFDQ setting. VREFDQ Calibration Mode may be exited when the DRAM is in idle state. After
the MRS command to exit VREFDQ Calibration Mode has been issued, DES must be issued till tVREFDQX has been
satisfied where any legal command may then be issued.
MRS
1
CMD CMD MRS CMD
CK#
CK
CMD
NOTE 1. The MR command used to enter VREFDQ Calibration Mode treats MR6 A [5:0] as don’t care while the next subsequent MR
command sets VREFDQ values in MR6 A[5:0] .
NOTE 2. Depending on the step size of the latest programmed VREF value, VREF_time must be satisfied before disabling VREFDQ training mode.
tVREFDQE
VREFDQ Training On
VREFDQ training mode
VREFDQ Training Off
tVREFDQX
Figure 47. V
REFDQ
training mode entry and exit timing diagram
AS4C256M16D4
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Rev.1.0 Aug.2019