Datasheet

Ball Descriptions
Table 3. Ball Details
Symbol
Type
Description
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input
signals are sampled on the crossing of the positive edge of CK and the negative
edge of CK#.
CKE
Input
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals
and device input buffers and output drivers. Taking CKE low provides Precharge
Power Down and Self-Refresh operation (all banks idle), or Active Power Down (row
Active in any bank). CKE is asynchronous for Self-Refresh exit. After V
REFCA
and
Internal DQ V
REF
have become stable during the power on and initialization sequence,
they must be maintained during all operations (including Self-Refresh). CKE must be
maintained high throughout read and write accesses. Input buffers, excluding CK,
CK#, ODT and CKE, are disabled during power down. Input buffers, excluding CKE,
are disabled during Self-Refresh.
CS#
Input
Chip Select: All commands are masked when CS# is registered high. CS# provides
for external Rank selection on systems with multiple Ranks. CS# is considered part
of the command code.
ODT
Input
On Die Termination: ODT (registered high) enables R
TT_NOM
termination resistance
internal to the DDR4 SDRAM. When enabled, ODT is applied to each DQ, LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM signal. The ODT pin will be ignored if MR1
is programmed to disable R
TT_NOM
.
ACT#
Input
Activation Command Input: ACT# defines the Activation command being entered
along with CS#. The input into RAS#/A16, CAS#/A15 and WE#/A14 will be considered
as Row Address A16, A15 and A14.
RAS#/A16
CAS#/A15
WE#/A14
Input
Command Inputs: RAS#/A16, CAS#/A15 and WE#/A14 (along with CS#) define the
command being entered. Those pins have multi function. For example, for activation
with ACT# low, those are Addressing like A16, A15 and A14 but for non-activation
command with ACT# high, those are Command pins for Read, Write and other
command defined in command truth table.
LDM#/LDBI#
UDM#/UDBI#
Input /
Output
Input Data Mask and Data Bus Inversion: DM# is an input mask signal for write
data. Input data is masked when DM# is sampled low coincident with that input data
during a Write access. DM# is sampled on both edges of DQS. DM is muxed with
DBI function by Mode Register A10, A11, A12 setting in MR5. DBI# is an input
/output identifying whether to store/output the true or inverted data. If DBI# is low the
data will be stored/output after inversion inside the DDR4 SDRAM and not inverted if
DBI# is high.
BG0
Input
Bank Group Inputs: BG0 define to which bank group an Active, Read, Write or
Precharge command is being applied. BG0 also determines which mode register is
to be accessed during a MRS cycle.
BA0-BA1
Input
Bank Address: BA0-BA1 define to which bank an Active, Read, Write, or Precharge
command is being applied. Bank address also determines which mode register is to
be accessed during a MRS cycle.
A0-A16
Input
Address Inputs: Provide the row address for Activate Commands and the column
address for Read/Write commands to select one location out of the memory array in
the respective bank. (A10/AP, A12/BC#, RAS#/A16, CAS#/A15 and WE#/A14 have
additional functions, see other rows. The address inputs also provide the op-code
during Mode Register Set commands. A15 and A16 are used on some higher densities.
A10/AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write
operation. (high: Autoprecharge; low: no Autoprecharge). A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10
low) or all banks (A10 high). If only one bank is to be precharged, the bank is selected
by bank addresses.
AS4C256M16D4
Confidential
- 6 of 201 -
Rev.1.0 Aug.2019