Datasheet
Data Mask (DM), Data Bus Inversion (DBI)
DDR4 SDRAM supports Data Mask (DM) function and Data Bus Inversion (DBI) function in x16 DRAM
configuration.
DM#, DBI# functions are supported with dedicated one pin labeled as DM#/DBI#/TDQS. The pin is bi-
directional pin for DRAM. The DM#/DBI# pin is Active Low as DDR4 supports V
DDQ
reference termination. DM,
DBI & TDQS functions are programmable through DRAM Mode Register (MR). The MR bit location is bit
A12:A10 in MR5.
Write operation: Either DM or DBI function can be enabled but both functions cannot be enabled simultanteously.
When both DM and DBI functions are disabled, DRAM turns off its input receiver and does not expect any
valid logic level.
Read operation: Only DBI function applies. When DBI function is disabled, DRAM turns off its output driver
and does not drive any valid logic level.
Table 23. DM vs. DBI Function Matrix
DM (MR5 bit A10)
Write DBI (MR5 bit A11)
Read DBI (MR5 bit A12)
Enabled
Disabled
Enabled or Disabled
Disabled
Enabled
Enabled or Disabled
Disabled
Disabled
Enabled or Disabled
Disabled
Disabled
Disabled
DM function during Write operation: DRAM masks the write data received on the DQ inputs if DM# was
sampled Low on a given byte lane. If DM# was sampled High on a given byte lane, DRAM does not mask the
write data and writes into the DRAM core.
DBI function during Write operation: DRAM inverts write data received on the DQ inputs if DBI# was
sampled Low on a given byte lane. If DBI# was sampled High on a given byte lane, DRAM leaves the data
received on the DQ inputs non-inverted.
DBI function during Read operation: DRAM inverts read data on its DQ outputs and drives DBI# pin Low
when the number of ‘0’ data bits within a given byte lane is greater than 4; otherwise DRAM does not invert
the read data and drives DBI# pin High.
Table 24. DQ Frame Format
Write
Data transfer
0
1
2
3
4
5
6
7
DQ[7:0]
LByte 0
LByte 1
LByte 2
LByte 3
LByte 4
LByte 5
LByte 6
LByte 7
LDM# or LDBI#
LDM0 or
LDBI0
LDM1 or
LDBI1
LDM2 or
LDBI2
LDM3 or
LDBI3
LDM4 or
LDBI4
LDM5 or
LDBI5
LDM6 or
LDBI6
LDM7 or
LDBI7
DQ[15:8]
UByte 0
UByte 1
UByte 2
UByte 3
UByte 4
UByte 5
UByte 6
UByte 7
UDM# or UDBI#
UDM0 or
UDBI0
UDM1 or
UDBI1
UDM2 or
UDBI2
UDM3 or
UDBI3
UDM4 or
UDBI4
UDM5 or
UDBI5
UDM6 or
UDBI6
UDM7 or
UDBI7
Read
Data transfer
0
1
2
3
4
5
6
7
DQ[7:0]
LByte 0
LByte 1
LByte 2
LByte 3
LByte 4
LByte 5
LByte 6
LByte 7
LDBI#
LDBI0
LDBI1
LDBI2
LDBI3
LDBI4
LDBI5
LDBI6
LDBI7
DQ[15:8]
UByte 0
UByte 1
UByte 2
UByte 3
UByte 4
UByte 5
UByte 6
UByte 7
UDBI#
UDBI0
UDBI1
UDBI2
UDBI3
UDBI4
UDBI5
UDBI6
UDBI7
AS4C256M16D4
Confidential
- 58 of 201 -
Rev.1.0 Aug.2019