Datasheet

Control Gear-down Mode
The following description represents the sequence for the gear-down mode which is specified with MR3 A[3].
This mode is allowed just during initialization and self refresh exit. The DRAM defaults in 1/2 rate (1N) clock
mode and utilizes a low frequency MRS command followed by a sync pulse to align the proper clock edge for
operating the control lines CS#, CKE and ODT in 1/4rate(2N) mode. For operation in 1/2 rate mode MRS
command for geardown or sync pulse are not required. DRAM defaults in 1/2 rate mode.
General sequence for operation in geardown during initialization
- DRAM defaults to a 1/2 rate (1N mode) internal clock at power up/reset
- Assertion of Reset
- Assertion of CKE enables the DRAM
- MRS is accessed with a low frequency N x t
CK
geardown MRS command. (Nt
CK
static MRS command
qualified by 1N CS#)
- DRAM controller sends 1N sync pulse with a low frequency N x t
CK
NOP command. tSYNC_GEAR is an even
number of clocks. The sync pulse on even clock boundary from MRS command.
- Initialization sequence, including the expiration of t
DLLK
and t
ZQinit
, starts in 2N mode after tCMD_GEAR from 1N
Sync Pulse.
General sequence for operation in gear-down after self refresh exit
- DRAM reset to 1N mode during self refresh
- MRS is accessed with a low frequency N x t
CK
gear-down MRS command. (Nt
CK
static MRS command
qualified by 1N CS# which meets tXS or tXS_Abort Only Refresh command is allowed to be issued to DRAM
before Nt
CK
static MRS command.
- DRAM controller sends 1N sync pulse with a low frequency N x t
CK
NOP command. tSYNC_GEAR is an even
number of clocks Sync pulse is on even clock boundary from MRS command.
- Valid command not requiring locked DLL is available in 2N mode after tCMD_GEAR from 1N Sync Pulse.
- Valid command requiring locked DLL is available in 2N mode after t
DLLK
from 1N Sync Pulse.
If operation is 1/2 rate(1N) mode after self refresh, no N x t
CK
MRS command or sync pulse is required
during self refresh exit. The min exit delay is tXS or tXS_Abort to the first valid command.
The DRAM may be changed from 1/4 rate ( 2N ) to 1/2 rate ( 1N ) by entering Self Refresh Mode, which will
reset to 1N automatically. Changing from 1/4 ( 2N ) to 1/2 rate (1 N ) by any other means, including setting
MR3[A3] from 1 to 0, can result in loss of data and operation of the DRAM uncertain.
For the operation of geardown mode in 1/4 rate, the following MR settings should be applied.
CAS Latency (MR0 A[6:4,2]) : Even number of clocks
Write Recovery and Read to Precharge (MR0 A[11:9]) : Even number of clocks
Additive Latency (MR1 A[4:3]) : 0, CL -2
CAS Write Latency (MR2 A[5:3]) : Even number of clocks
CS to Command/Address Latency Mode (MR4 A[8:6]): Even number of clocks
CA Parity Latency Mode (MR5 A[2:0]) : Even number of clocks
CAL or CA parity mode must be disabled prior to Gear down MRS command. They can be enabled again after
tSYNC_GEAR and tCMD_GEAR periods are satisfied.
The diagram below illustrates the sequence for control operation in 2N mode during intialization.
CK#
CK
DON'T CARE
DRAM
(Internal)
CLK
CS#
CMD
CKE
1N Sync Pulse 2N Mode
Reset
NOTE 1. Only DES is allowed during t
SYNC_GEAR
.
MRS
t
CKSRX
t
XPR_GEAR
t
SYNC_GEAR
t
CMD_GEAR
t
GEAR_setup
t
GEAR_hold
Configure DRAM
to 1/4 rate
t
GEAR_setup
t
GEAR_hold
TdkN TdkN + Neven
NOP
VALID
Figure 39. Gear down (2N) mode entry sequence during initialization
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019