Datasheet

Power down Mode
Power-down is synchronously entered when CKE is registered low (along with Deselect command). CKE is
not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or
Read / Write operation are in progress. CKE is allowed to go low while any of other operations such as row
activation, precharge or auto-precharge and refresh are in progress, but power-down IDD spec will not be
applied until finishing those operations. Timing diagrams below illustrate entry and exit of power-down.
The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the
DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper
read operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage
specification as well as proper DLL operation with any CKE intensive operations as long as DRAM controller
complies with DRAM specifications.
During Power-Down, if all banks are closed after any in-progress commands are completed, the device will
be in precharge Power-Down mode; if any bank is open after in-progress commands are completed, the
device will be in active Power-Down mode.
Entering power-down deactivates the input and output buffers, excluding CK, CK#, CKE and RESET#. In
power-down mode, DRAM ODT input buffer deactivation is based on MR5 bit A5. If it is conured to 0b, ODT
input buffer remains on and ODT input signal must be at valid logic level. If it is configured to 1b, ODT input buffer
is deactivated and DRAM ODT input signal may be floating and DRAM does not provide R
TT_NOM
termination.
Note that DRAM continues to provide R
TT_PARK
termination if it is enabled in DRAM mode register MR5 A[8:6].
To protect DRAM internal delay on CKE line to block the input signals, multiple Deselect commands are needed
during the CKE switch off and cycle(s) after, this timing period are defined as t
CPDED
. CKE low will result in
deactivation of command and address receivers after t
CPDED
has expired.
Table 21. Power-Down Entry Definitions
Status of DRAM
DLL
PD Exit
Relevant Parameters
Active (A bank or more Open)
On
Fast
t
XP
to any valid command
Precharged (All banks precharged)
On
Fast
t
XP
to any valid command
Also, the DLL is kept enabled during precharge power-down or active power-down. In power-down mode,
CKE low, RESET# high, and a stable clock signal must be maintained at the inputs of the device, and ODT
should be in a valid state, but all other input signals are “Don’t Care.” (If RESET# goes low during Power-
Down, the device will be out of power-down mode and into reset state.) CKE low must be maintained until t
CKE
has been satisfied. Power-down duration is limited by 9 times t
REFI
.
The power-down state is synchronously exited when CKE is registered high (along with a Deselect
command). CKE high must be maintained until t
CKE
has been satisfied. The ODT input signal must be at valid
level when device exits from power-down mode independent of MR5 bit A5 if R
TT_NOM
is enabled in DRAM
mode register. If R
TT_NOM
is disabled then ODT input signal may remain floating. A valid, executable command
can be applied with power-down exit latency, t
XP
after CKE goes high. Power-down exit latency is defined in
the AC specifications table.
AS4C256M16D4
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Rev.1.0 Aug.2019