Datasheet

Self Refresh Abort
The exit timing from self-refresh exit to first valid command not requiring a locked DLL is t
XS
. The value of t
XS
is (t
RFC
+10ns). This delay is to allow for any refreshes started by the DRAM to complete. t
RFC
continues to
grow with higher density devices so t
XS
will grow as well.
A Bit A9 in MR4 is defined to enable the self refresh abort mode. If the bit is disabled then the controller
uses t
XS
timings. If the bit is enabled then the DRAM aborts any ongoing refresh and does not increment the
refresh counter. The controller can issue a valid command not requiring a locked DLL after a delay of t
XS_abort
.
Upon exit from Self-Refresh, the device requires a minimum of one extra refresh command before it is put
back into Self- Refresh Mode. This requirement remains the same irrespective of the setting of the MRS bit for
self refresh abort.
CK#
T1 Ta0 Tb0 Tc0 Td0 Td1 Te0 Tf0T0
CK
t
CKSRE
Tg0
t
CKESR /
t
CKESR_PAR
t
XS_ABORT
4
t
XSDLL
DES SRE DES VALID
2
VALID
1
VALID
VALID
ODT
CKE
CMD
ADDR
t
IS
NOTE 1. Only MRS (limited to those described in the Self-Refresh Operation section). ZQCS or ZQCL command allowed.
NOTE 2. Valid commands not requiring a locked DLL.
NOTE 3. Valid commands requiring a locked DLL.
NOTE 4. Only DES is allowed during t
XS_ABORT
.
t
CKSRX
VALID
t
CPDED
t
IS
VALID
SRX VALID
3
VALID
t
RP
ODTL
Enter Self Refresh Exit Self Refresh
VALID
t
XS_FAST
VALIDVALID
DON'T CARETIME BREAK
Figure 25. Self-Refresh Entry/Exit Timing
AS4C256M16D4
Confidential
- 44 of 201 -
Rev.1.0 Aug.2019