Datasheet

Self Refresh Operation
The Self-Refresh command can be used to retain data in the device, even if the rest of the system is
powered down. When in the Self-Refresh mode, the device retains data without external clocking. The device
has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh-Entry (SRE) Command is
defined by having CS#, RAS#/A16, CAS#/A15, and CKE held low with WE#/A14 and ACT# high at the rising
edge of the clock.
Before issuing the Self-Refresh-Entry command, the device must be idle with all bank precharge state with
t
RP
satisfied. Idle state is defined as all banks are closed (t
RP
, t
DAL
, etc. satisfied), no data bursts are in
progress, CKE is high, and all timings from previous operations are satisfied (t
MRD
, t
MOD
, t
RFC
, t
ZQini
t, t
ZQoper
,
t
ZQCS
, etc.). Deselect command must be registered on last positive clock edge before issuing Self Refresh
Entry command. Once the Self Refresh Entry command is registered, Deselect command must also be
registered at the next positive clock edge. Once the Self-Refresh Entry command is registered, CKE must be
held low to keep the device in Self-Refresh mode. DRAM automatically disables ODT termination and set Hi-Z
as termination state regardless of ODT pin and R
TT_PARK
set when it enters in Self-Refresh mode. Upon exiting
Self-Refresh, DRAM automatically enables ODT termination and set R
TT_PARK
asynchronously during t
XSDLL
when R
TT_PARK
is enabled. During normal operation (DLL on) the DLL is automatically disabled upon entering Self-
Refresh and is automatically enabled (including a DLL-Reset) upon exiting Self-Refresh.
When the device has entered Self-Refresh mode, all of the external control signals, except CKE and
RESET#, are “don’t care.” For proper Self-Refresh operation, all power supply and reference pins (V
DD
, V
DDQ
,
V
SS
, V
SSQ
, V
PP
, and V
REFCA
) must be at valid levels. DRAM internal V
REFDQ
generator circuitry may remain on or
turned off depending on the MR6 bit 7 setting. If DRAM internal V
REFDQ
circuitry is turned off in self refresh,
when DRAM exits from self refresh state, it ensures that V
REFDQ
generator circuitry is powered up and stable
within t
XS
period. First Write operation or first Write Leveling Activity may not occur earlier than t
XS
after exit
from Self Refresh. The DRAM initiates a minimum of one Refresh command internally within t
CKE
period once
it enters Self-Refresh mode.
The clock is internally disabled during Self-Refresh Operation to save power. The minimum time that the
DDR4 SDRAM must remain in Self-Refresh mode is t
CKESR
. The user may change the external clock
frequency or halt the external clock t
CKSRE
after Self- Refresh entry is registered, however, the clock must be
restarted and stable t
CKSRX
before the device can exit Self-Refresh operation.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior
to CKE going back high. Once a Self-Refresh Exit command (SRX, combination of CKE going high and
Deselect on command bus) is registered, following timing delay must be satisfied:
Commands that do not require locked DLL:
 t
XS
= ACT, PRE, PREA, REF, SRE, PDE, WR, WRS4, WRS8, WRA, WRAS4, WRAS8
 t
XSFast
= ZQCL, ZQCS, MRS commands. For MRS command, only DRAM CL and WR/RTP register and DLL
Reset in MR0, R
TT_NOM
register in MR1, CWL and R
TT_WR
register in MR2 and geardown mode in MR3, Write
and Read Preamble register in MR4, R
TT_PARK
register in MR5, t
CCD_L
/t
DLLK
and V
REFDQ
Training Value in MR6
are allowed to be accessed provided DRAM is not in per DRAM addressability mode. Access to other DRAM
mode registers must satisfy t
XS
timing. Note that synchronous ODT for write commands (WR, WRS4, WRS8,
WRA, WRAS4 and WRAS8) and dynamic ODT controlled by write command require locked DLL.
Commands that require locked DLL:
 t
XSDLL
- RD, RDS4, RDS8, RDA, RDAS4, RDAS8
Depending on the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands
may be required to compensate for the voltage and temperature drift as described in the ZQ Calibration
Commands section. To issue ZQ calibration commands, applicable timing requirements must be satisfied.
CKE must remain high for the entire Self-Refresh exit period t
XSDLL
for proper operation except for Self-
Refresh re-entry. Upon exit from Self-Refresh, the device can be put back into Self-Refresh mode or Power
down mode after waiting at least t
XS
period and issuing one refresh command (refresh period of t
RFC
). Deselect
commands must be registered on each positive clock edge during the Self-Refresh exit interval t
XS
. Low level
of ODT pin must be registered on each positive clock edge during t
XSDLL
when normal mode (DLL-on) is set.
Under DLL-off mode, asynchronous ODT function might be allowed.
The use of Self-Refresh mode introduces the possibility that an internally timed refresh event can be missed
when CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the device requires a
minimum of one extra refresh command before it is put back into Self-Refresh Mode.
AS4C256M16D4
Confidential
- 43 of 201 -
Rev.1.0 Aug.2019