Datasheet

Procedure Description
The Memory controller initiates Leveling mode of all DRAMs by setting bit A7 of MR1 to 1. When entering
write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode, only Deselect
commands are allowed, as well as an MRS command to change Qoff bit (MR1[A12]) and an MRS command
to exit write leveling (MR1[A7]). Upon exiting write leveling mode, the MRS command performing the exit
(MR1[A7]=0) may also change the other MR1 bits. Since the controller levels one rank at a time, the output of
other ranks must be disabled by setting MR1 bit A12 to 1. The Controller may assert ODT after t
MOD
, at which
time the DRAM is ready to accept the ODT signal.
The Controller may drive DQS low and DQS# high after a delay of t
WLDQSEN
, at which time the DRAM has
applied on-die termination on these signals. After t
DQSL
and t
WLMRD
, the controller provides a single DQS, DQS#
edge which is used by the DRAM to sample CK - CK# driven from controller. t
WLMRD(max)
timing is controller
dependent.
DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on all the DQ bits
asynchronously after t
WLO
timing. There is a DQ output uncertainty of t
WLOE
defined to allow mismatch on DQ
bits. The t
WLOE
period is defined from the transition of the earliest DQ bit to the corresponding transition of the
latest DQ bit. There are no read strobes (DQS/DQS#) needed for these DQs. Controller samples incoming
DQs and decides to increment or decrement DQS - DQS# delay setting and launches the next DQS - DQS#
pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the controller locks
DQS - DQS# delay setting and write leveling is achieved for the device. The following figure shows the timing
diagram and parameters for the overall Write Leveling procedure.
t
WLMRD
DON'T CARETIME BREAK
DES
(3)
MRS
(2)
DES DES DES DES DES DES DES DES DES
t
WLS
t
WLH
Ta
t
WLS
t
WLH
Tb
DES
t
WLDQSEN
(8)
t
DQSL
(6)
t
DQSH
(6)
t
DQSL
(6)
t
DQSH
(6)
t
WLOE
t
WLO
t
MOD
(7)
t
WLO
t
WLMRD
t
WLO
t
WLO
t
WLOE
INVALID
NOTE 1. DDR4 SDRAM drives leveling feedback on all DQs.
NOTE 2. MRS: Load MR1 to enter write leveling mode.
NOTE 3. DES: Deselect.
NOTE 4. diff_DQS is the differential data strobe (DQS-DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown with dotted line.
NOTE 5. CK/CK#: CK is shown with solid dark line, where as CK# is drawn with dotted line.
NOTE 6. DQS, DQS# needs to fulfill minimum pulse width requirements t
DQSH(min)
and t
DQSL(min)
as defined for regular Writes; the max pulse width is system dependent.
NOTE 7. t
MOD(Min)
= max(24nCK, 15ns), WL = 9 (CWL = 9, AL = 0, PL = 0), DODTLon = WL -2 = 7.
NOTE 8. t
WLDQSEN
must be satisfied following equation when using ODT.
t
WLDQSEN
> t
MOD(Min)
+ ODTLon + t
ADC
: at DLL = Enable
t
WLDQSEN
> t
MOD(Min)
+ t
AONAS
: at DLL = Disable
T0 T24 T31
DODTLon
(7)
t
ADC
CK#
(5)
CK
CMD
ODT
Diff_DQS
(4)
Late DQs
(1)
Early DQs
(1)
RTT
DES DES
VALID
Figure 13. Write Leveling Sequence (DQS capturing CK low at Ta and CK high at Tb)
AS4C256M16D4
Confidential
- 34 of 201 -
Rev.1.0 Aug.2019