Datasheet

DRAM setting for write leveling & DRAM termination function in that mode
DRAM enters into Write leveling mode if A7 in MR1 set ’High’ and after finishing leveling, DRAM exits from
write leveling mode if A7 in MR1 set ’Low’ (see the MR setting involved in the leveling procedure table). Note
that in write leveling mode, only DQS terminations are activated and deactivated via ODT pin, unlike normal
operation (see the DRAM termination function in the leveling mode table).
Table 15. MR setting involved in the leveling procedure
Function
MR1
Enable
Disable
Write leveling enable
A7
1
0
Output buffer mode (Qoff)
A12
0
1
Table 16. DRAM termination function in the leveling mode
ODT pin @DRAM if R
TT_NOM
/
PARK
Value is set via MRS
DQS/DQS# termination
DQs termination
R
TT_NOM
with ODT High
on
off
R
TT_PARK
with ODT Low
on
off
Notes:
1. In Write Leveling Mode with its output buffer disabled (MR1[bit A7] = 1 with MR1[bit A12] = 1) all R
TT_NOM
and R
TT_PARK
settings are
allowed; in Write Leveling Mode with its output buffer enabled (MR1[bit A7] = 1 with MR1[bit A12] = 0) all R
TT_NOM
and R
TT_PARK
settings
are allowed.
2. Dynamic ODT function is not available in Write Leveling Mode. DRAM MR2 bits A[11:9] must be ‘000’ prior to entering Write Leveling
Mode.
AS4C256M16D4
Confidential
- 33 of 201 -
Rev.1.0 Aug.2019