Datasheet

Write Leveling
For better signal integrity, the DDR4 memory module adopted fly-by topology for the commands, addresses,
control signals, and clocks. The fly-by topology has benefits from reducing number of stubs and their length,
but it also causes flight time skew between clock and strobe at every DRAM on the DIMM. This makes it
difficult for the Controller to maintain t
DQSS
, t
DSS
, and t
DSH
specification. Therefore, the device supports a write
leveling feature to allow the controller to compensate for skew. This feature may not be required under some
system conditions provided the host can maintain the t
DQSS
, t
DSS
and t
DSH
specifications.
The memory controller can use the write leveling feature and feedback from the device to adjust the DQS,
DQS# to CK, CK# relationship. The memory controller involved in the leveling must have adjustable delay
setting on DQS, DQS# to align the rising edge of DQS, DQS# with that of the clock at the DRAM pin. The
DRAM asynchronously feeds back CK, CK#, sampled with the rising edge of DQS, DQS#, through the DQ
bus. The controller repeatedly delays DQS, DQS# until a transition from 0 to 1 is detected. The DQS, DQS#
delay established through this exercise would ensure t
DQSS
specification.
Besides t
DQSS
, t
DSS
and t
DSH
specification also needs to be fulfilled. One way to achieve this is to combine
the actual t
DQSS
in the application with an appropriate duty cycle and jitter on the DQS, DQS# signals.
Depending on the actual t
DQSS
in the application, the actual values for t
DQSL
and t
DQSH
may have to be better
than the absolute limits provided in the chapter "AC Timing Parameters" in order to satisfy t
DSS
and t
DSH
specification. A conceptual timing of this scheme is shown below.
CK#
T1 T2 T3 T4 T5 T6 T7T0
CK
Diff_DQS
DQ
Source
Destination
T0 T1 T2 T3 T4 T5 T6Tn
CK#
CK
Diff_DQS
0
DQ
Diff_DQS
1
Push DQS to capture 0-1
transition
0
1
1
00 or 1
0 or 1
Figure 12. Write Leveling Concept
DQS, DQS# driven by the controller during leveling mode must be terminated by the DRAM based on ranks
populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
All data bits should carry the leveling feedback to the controller across the DRAM configurations x16. On a
x16 device, both byte lanes should be leveled independently. Therefore, a separate feedback mechanism should
be available for each byte lane. The upper data bits should provide the feedback of the upper
diff_DQS(diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower
diff_DQS(diff_LDQS) to clock relationship.
AS4C256M16D4
Confidential
- 32 of 201 -
Rev.1.0 Aug.2019