Datasheet

Input Clock Frequency Change
After the device is initialized, the DDR4 SDRAM requires the clock to be “stable” during almost all states of
normal operation. This means that after the clock frequency has been set and is to be in the “stable state”, the
clock period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread
spectrum clocking) specifications. The input clock frequency can be changed from one stable clock rate to
another stable clock rate only when in Self- Refresh mode. Outside Self-Refresh mode, it is illegal to change
the clock frequency.
After the device has been successfully placed into Self-Refresh mode and t
CKSRE
has been satisfied, the state
of the clock becomes a "Don’t Care". Following a "Don’t Care", changing the clock frequency is permissible,
provided the new clock frequency is stable prior to t
CKSRX
. When entering and exiting Self-Refresh mode for
the sole purpose of changing the clock frequency, the Self-Refresh entry and exit specifications must still be
met as outlined in Self-Refresh Operation.
For the new clock frequency, additional MRS commands to MR0, MR2, MR3, MR4, MR5, and MR6 may
need to be issued to program appropriate CL, CWL, Gear-down mode, Read & Write Preamble, Command
Address Latency (CAL Mode), Command Address Parity (CA Parity Mode), and t
CCD_L
/t
DLLK
value.
In particular, the Command Address Parity Latency (PL) must be disabled when the clock rate changes, ie.
while in Self Refresh Mode. For example, if changing the clock rate from DDR4-2133 to DDR4-2666 with CA
Parity Mode enabled, MR5[2:0] must first change from PL = 4 to PL = disable prior to PL = 5. The correct
procedure would be to (1) change PL = 4 to disable via MR5 [2:0], (2) enter Self Refresh Mode, (3) change
clock rate from DDR4-2133 to DDR4-2666, (4) exit Self Refresh Mode, (5) Enable CA Parity Mode setting PL
= 5 via MR5 [2:0].
If the MR settings that require additional clocks are updated after the clock rate has been increased, i.e.
after exiting self refresh mode, the required MR settings must be updated prior to removing the DRAM from
the idle state, unless the DRAM is reset. If the DRAM leaves the idle state to enter self refresh mode or ZQ
Calibration, the updating of the required MR settings may be deferred to after the next time the DRAM enters
the idle state.
If MR6 is issued prior to Self Refresh Entry for new t
DLLK
value, then DLL will relock automatically at Self
Refresh Exit. However, if MR6 is issued after Self Refresh Entry, then MR0 must be issued to reset the DLL.
The device input clock frequency can change only within the minimum and maximum operating frequency
specified for the particular speed grade. Any frequency change below the minimum operating frequency would
require the use of DLL-on mode to DLL-off mode transition sequence. (See DLL on/off switching procedure)
AS4C256M16D4
Confidential
- 31 of 201 -
Rev.1.0 Aug.2019