Datasheet

DLL-off Mode
DLL-off mode is entered by setting MR1 bit A0 to “0”; this will disable the DLL for subsequent operations
until A0 bit is set back to “1”. The MR1 A0 bit for DLL control can be switched either during initialization or
during self refresh mode. Refer to the Input Clock Frequency Change section for more details.
The maximum clock frequency for DLL-off Mode is specified by the parameter t
CKDLL_OFF
. There is no
minimum frequency limit besides the need to satisfy the refresh interval, t
REFI
.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write
Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of both CL=10 and
CWL=9.
DLL-off mode will affect the Read data Clock to Data Strobe relationship (t
DQSCK
), but not the Data Strobe to
Data relationship (t
DQSQ
, t
QH
). Special attention is needed to line up Read data to controller time domain.
Comparing with DLL-on mode, where t
DQSCK
starts from the rising clock edge (AL+CL) cycles after the Read
command, the DLL-off mode t
DQSCK
starts (AL+CL - 1) cycles after the read command. Another difference is
that t
DQSCK
may not be small compared to t
CK
(it might even be larger than t
CK
) and the difference between
t
DQSCKmin
and t
DQSCKmax
is significantly larger than in DLL-on mode. t
DQSCK(DLL_off)
values are undefined.
The timing relations on DLL-off mode Read operation are shown in the following diagram, where CL = 10,
AL = 0, and BL = 8.
T1 T6 T7 T8 T9 T10 T11 T12 T13T0 T14
RL = AL + CL = 10 (CL = 10, AL = 0)
CL = 10
QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7
QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7
QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7
RL (DLL_off) = AL + (CL-1) = 9
t
DQSCK(DLL_off)_min
t
DQSCK(DLL_off)_max
CK#
BA
CK
CMD
DQSdiff_DLL_on
DQ_DLL_on
DQ_DLL_off
DQSdiff_DLL_off
DQ_DLL_off
DQSdiff_DLL_off
READ
A
Figure 11. Read operation at DLL-off mode
AS4C256M16D4
Confidential
- 30 of 201 -
Rev.1.0 Aug.2019