Datasheet

DLL-off Mode and DLL on/off Switching Procedure
DLL on/off switching procedure
The DLL-off mode is entered by setting MR1 bit A0 to “0”; this will disable the DLL for subsequent
operations until A0 bit is set back to “1”.
DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh, as outlined
in the following procedure:
1. Starting from Idle state (All banks pre-charged, all timings fulfilled, and DRAMs On-die Termination resistors,
R
TT_NOM
, must be in high impedance state before MRS to MR1 to disable the DLL.)
2. Set MR1 bit A0 to “0” to disable the DLL.
3. Wait t
MOD
.
4. Enter Self Refresh Mode; wait until (t
CKSRE
) is satisfied.
5. Change frequency, following the guidelines in the Input Clock Frequency Change section.
6. Wait until a stable clock is available for at least (t
CKSRX
) at device inputs.
7. Starting with the Self Refresh Exit command, CKE must continuously be registered high until all t
MOD
timings
from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers
when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until all t
MOD
timings from any MRS command are satisfied. If R
TT_NOM
features were disabled in the mode registers when
Self Refresh mode was entered, ODT signal is Don’t Care.
8. Wait t
XS_Fast
or t
XS_Abort
or t
XS
, then set Mode Registers with appropriate values (especially an update of CL,
CWL and WR may be necessary; a ZQCL command may also be issued after t
XS_Fast)
.
 t
XS_Fast
: ZQCL, ZQCS, MRS commands. For MRS command, only CL and WR/RTP register in MR0,
CWL register in MR2 and geardown mode in MR3 are allowed to be accessed provided the device is not
in per DRAM addressibility mode. Access to other device mode registers must satisfy t
XS
timing.
 t
XS_Abort
: If the MR4 bit A9 is enabled then the device aborts any ongoing refresh and does not increment
the refresh counter. The controller can issue a valid command after a delay of t
XS_Abort
. Upon exit from
Self-Refresh, the device requires a minimum of one extra refresh command before it is put back into
Self-Refresh Mode. This requirement remains the same irrespective of the setting of the MRS bit for self
refresh abort.
 t
XS
: ACT, PRE, PREA, REF, SRE, PDE, WR, WRS4, WRS8, WRA, WRAS4, WRAS8, RD, RDS4, RDS8,
RDA, RDAS4, RDAS8
9. Wait for t
MOD
, then device is ready for next command.
Tb0 Tb4 Tc Td Te0 Te1 Tf Tg ThTa
SRE
3
MRS
2
DES VALID
7
VALID
8
VALID
9
t
CKSRE
Notes 4
t
CKSRX
5
t
XS_FAST
t
XS_ABORT
t
CKESR
t
IS
Exit Self Refresh
VALID VALID VALID
t
CPDED
t
IS
VALID
VALID VALID VALID VALID
Enter Self Refresh
CK#
CK
CMD
CKE
ODT
ADDR
t
RP
DON'T CARETIME BREAK
SRX
6
t
XS
Notes:
1. Starting with Idle State, R
TT
in Stable
2. Disable DLL by setting MR1 Bit A0 to 0
3. Enter SR
4. Change Frequency
5. Clock must be stable t
CKSRX
6. Exit SR
7.8.9. Update Mode registers allowed with DLL off parameters setting
Figure 9. DLL Switch Sequence from DLL ON to DLL OFF
AS4C256M16D4
Confidential
- 28 of 201 -
Rev.1.0 Aug.2019