Datasheet

CA Parity Error Status
The device will set the error status bit to 1 upon detecting a parity error. The parity error status bit remains
set at 1 until the device controller clears it explicitly using an MRS command.
CRC Error Clear
The device will set the error status bit to 1 upon detecting a CRC error. The CRC error status bit remains set
at 1 until the device controller clears it explicitly using an MRS command.
CA Parity Latency Mode
CA parity is enabled when a latency value, dependent on t
CK
, is programmed; this accounts for parity
calculation delay internal to the device. The normal state of CA parity is to be disabled. If CA parity is enabled,
the device must ensure there are no parity errors before executing the command. CA parity signal (PAR)
covers ACT#, RAS#/A16, CAS#/A15, WE#/A14, and the address bus including bank address and bank group
bits. The control signals CKE, ODT, and CS# are not included in the parity calculation.
AS4C256M16D4
Confidential
- 25 of 201 -
Rev.1.0 Aug.2019