Datasheet
Mode Register MR5
Table 13. MR5 Definition
BG0
BA1
BA0
RAS#
/A16
CAS#
/A15
WE#/
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
0
1
0
0
0
0
*1
RDBI
WDBI
DM
CAPE
R
TT_PARK
ODT IB
for PD
Parity
Error
CRC
error
C/A Parity Latency
Note 1. Reserved for future use and must be programmed to 0 during MRS.
Note 2. When R
TT_NOM
Disable is set in MR1, A5 of MR5 will be ignored.
Data Bus Inversion
The Data Bus Inversion (DBI) function has been added to the device and is supported for x16 configurations.
The DBI function shares a common pin with the DM functions. The DBI function applies to both Read and
Write operations; Write DBI cannot be enabled at the same time the DM function is enabled. DBI is not
allowed during MPR Read operation; during an MPR read, the DRAM ignores the read DBI enable setting in
MR5 bit A12.
Data Mask
The Data Mask (DM) function, also described as a partial write, has been added to the device and is supported
for x16 configurations. The DM function shares a common pin with the DBI functions. The DM function applies only
to Write operations and cannot be enabled at the same time the write DBI function is enabled.
CA Parity Persistent Error Mode
Normal CA parity mode (CA parity persistent mode disabled) no longer performs CA parity checking while
the parity error status bit remains set at 1. However, with CA parity persistent mode enabled, CA parity checking
continues to be performed when the parity error status bit is set to a 1.
ODT Input Buffer for Power-Down
This feature determines whether the ODT input buffer is on or off during power-down. If the input buffer is
configured to be on (enabled during power-down), the ODT input signal must be at a valid logic level. If the
input buffer is configured to be off (disabled during power-down), the ODT input signal may be floating and the
device does not provide R
TT_NOM
termination. However, the device may provide R
TT_PARK
termination
depending on the MR settings. This is primarily for additional power savings.
A9
CA parity Persistent Error
A8
A7
A6
R
TT_PARK
A2
A1
A0
PL
0
Disable
0
0
0
R
TT_PARK
Disabled
0
0
0
Disabled
1
Enable
0
0
1
RZQ/4
0
0
1
4 (DDR4-1600/1866/2133)
0
1
0
RZQ/2
0
1
0
5 (DDR4-2400/2666)
A10
Data Mask
0
1
1
RZQ/6
0
1
1
Reserved
0
Disable
1
0
0
RZQ/1
1
0
0
Reserved
1
Enable
1
0
1
RZQ/5
1
0
1
Reserved
1
1
0
RZQ/3
1
1
0
Reserved
A11
Write DBI
1
1
1
RZQ/7
1
1
1
Reserved
0
Disable
1
Enable
A5
ODT Input Buffer during Power Down
*2
A4
C/A Parity Error Status
A3
CRC Error Clear
0
ODT input buffer is activated
0
Clear
0
Clear
A12
Read DBI
1
ODT input buffer is deactivated
1
Error
1
Error
0
Disable
1
Enable
AS4C256M16D4
Confidential
- 24 of 201 -
Rev.1.0 Aug.2019