Datasheet

Write Command Latency When CRC/DM is Enabled
The Write command latency (WCL) must be set when both Write CRC and DM are enabled for Write CRC
persistent mode. This provides the extra time required when completing a Write burst when Write CRC and
DM are enabled.
Fine Granularity Refresh Mode
This mode had been added to DDR4 to help combat the performance penalty due to refresh lockout at high
densities. Shortening t
RFC
and decreasing cycle time allows more accesses to the chip and allows for increased
scheduling flexibility.
Temperature Sensor Status
This mode directs the DRAM to update the temperature sensor status at MPR Page 2, MPR0 [4,3]. The
temperature sensor setting should be updated within 32ms; when an MPR read of the temperature sensor
status bits occurs, the temperature sensor status should be no older than 32ms.
Per-DRAM Addressability
The MRS command mask allows programmability of a given device that may be in the same rank (devices
sharing the same command and address signals). As an example, this feature can be used to program
different ODT or V
REF
values on DRAM devices within a given rank.
Gear-Down Mode
The device defaults in 1/2 rate (1N) clock mode and uses a low frequency MRS command followed by a
sync pulse to align the proper clock edge for operating the control lines CS#, CKE, and ODT when in 1/4 rate
(2N) mode. For operation in 1/2 rate mode, no MRS command or sync pulse is required.
AS4C256M16D4
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Rev.1.0 Aug.2019