Datasheet

Command, Control, and Address Setup, Hold, and Derating
The total t
IS
(setup time) and t
IH
(hold time) required is calculated to account for slew rate variation by adding
the data sheet t
IS(base)
values, the V
IL(AC)
/V
IH(AC)
points, and t
IH(base)
values, the V
IL(DC)
/V
IH(DC)
points; to the Δt
IS
and
Δt
IH
derating values, respectively. The base values are derived with single-end signals at 1V/ns and differential
clock at 2V/ns. Example: t
IS
(total setup time) = t
IS(base)
+ Δt
IS
. For a valid transition, the input signal has to remain
above/below V
IH(AC)
/V
IL(AC)
for the time defined by t
VAC
.
Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have
reached V
IH(AC)
/V
IL(AC)
at the time of the rising clock transition), a valid input signal is still required to complete
the transition and to reach V
IH(AC)
/V
IL(AC)
. For slew rates that fall between the values listed in derating tables,
the derating values may be obtained by linear interpolation.
Setup (t
IS
) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
IL(DC)max
and the first crossing of V
IH(AC)min
that does not ring back below V
IH(DC)min
. Setup (t
IS
) nominal slew rate for a
falling signal is defined as the slew rate between the last crossing of V
IH(DC)min
and the first crossing of V
IL(AC)max
that does not ring back above V
IL(DC)max
.
Hold (t
IH
) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
IL(DC)max
and the first crossing of V
IH(AC)min
that does not ring back below V
IH(DC)min
. Hold (t
IH
) nominal slew rate for a
falling signal is defined as the slew rate between the last crossing of V
IH(DC)min
and the first crossing of V
IL(AC)min
that does not ring back above V
IL(DC)max
.
Table 112. Command, Address, Control Setup and Hold Values
Symbol
Reference
DDR4-2400
DDR4-2666
Unit
t
IS(base, AC100)
V
IH(AC)
/V
IL(AC)
62
TBD
ps
t
IH(base, DC75)
V
IH(DC)
/V
IL(DC)
87
TBD
ps
t
IS
/t
IH(VREF)
-
162
TBD
ps
Note 1. Base ac/dc referenced for 1V/ns slew rate and 2 V/ns clock slew rate.
Note 2. Values listed are referenced only; applicable limits are defined elsewhere.
Table 113. Command, Address, Control Input Voltage Values
Symbol
Reference
DDR4-2400
DDR4-2666
Unit
V
IH.CA(AC)min
V
IH(AC)
/V
IL(AC)
100
TBD
mV
V
IH.CA(DC)min
V
IH(DC)
/V
IL(DC)
75
TBD
mV
V
IL.CA(AC)max
V
IH(AC)
/V
IL(AC)
-75
TBD
mV
V
IL.CA(DC)max
V
IH(DC)
/V
IL(DC)
-100
TBD
mV
Note 1. Command, Address, Control input levels relative to V
REFCA
.
Note 2. Values listed are referenced only; applicable limits are defined elsewhere.
Table 114. Derating values DDR4-2400 tIS/tIH – AC/DC based
󰅿t
IS
, 󰅿t
IH
derating in [ps] AC/DC based -- V
IH(AC)
/V
IL(AC)
= ±100mV, V
IH(DC)
/V
IL(DC)
= ±75mV; relative to V
REFCA
CK, CK# Differential Slew Rate
10.0 V/ns
8.0 V/ns
6.0 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.5 V/ns
1.0 V/ns
󰅿tIS
󰅿tIH
󰅿tIS
󰅿tIH
󰅿tIS
󰅿tIH
󰅿tIS
󰅿tIH
󰅿tIS
󰅿tIH
󰅿tIS
󰅿tIH
󰅿tIS
󰅿tIH
󰅿tIS
󰅿tIH
CMD,
ADDR,
CNTL
Input
Slew
rate
V/ns
7.0
76
54
76
55
77
56
79
58
82
60
86
64
94
73
111
89
6.0
73
53
74
53
75
54
77
56
79
58
83
63
92
71
108
88
5.0
70
50
71
51
72
52
74
54
76
56
80
60
88
68
105
85
4.0
65
46
66
47
67
48
69
50
71
52
75
56
83
65
100
81
3.0
57
40
57
41
58
42
60
44
63
46
67
50
75
58
92
75
2.0
40
28
41
28
42
29
44
31
46
33
50
38
58
46
75
63
1.5
23
15
24
16
25
17
27
19
29
21
33
25
42
33
58
50
1.0
-10
-10
-9
-9
-8
-8
-6
-6
-4
-4
0
0
8
8
25
25
0.9
-17
-14
-16
-14
-15
-13
-13
-10
-11
-8
-7
-4
1
4
18
21
0.8
-26
-19
-25
-19
-24
-18
-22
-16
-20
-14
-16
-9
-7
-1
9
16
0.7
-37
-26
-36
-25
-35
-24
-33
-22
-31
-20
-27
-16
-18
-8
-2
9
0.6
-52
-35
-51
-34
-50
-33
-48
-13
-46
-29
-42
-25
-33
-17
-17
-0
0.5
-73
-48
-72
-47
-71
-46
-69
-44
-67
-42
-63
-38
-54
-29
-38
-13
0.4
-104
-66
-103
-66
-102
-65
-100
-63
-98
-60
-94
-56
-85
-48
-69
-31
AS4C256M16D4
Confidential
- 199 of 201 -
Rev.1.0 Aug.2019