Datasheet

Slew Rate Definitions for Differential Input Signals (CK)
Table 104. Differential Input Slew Rate Definition
Description
Measured
Defined by
From
To
Differential input slew rate for rising edge (CK - CK#)
V
ILdiffmax
V
IHdiffmin
IHdiffmin
– V
ILdiffmax
Differential input slew rate for falling edge (CK - CK#)
V
IHdiffmin
V
ILdiffmax
IHdiffmin
– V
ILdiffmax
Note 1. The differential signal (i,e., CK - CK#) must be linear between these thresholds.
Differential Input Cross Point Voltage
Table 105. Cross point voltage for differential input signals (CK)
Symbol
Parameter
DDR4-2400/2666
Min.
Max.
-
Area of V
SEH
, V
SEL
TBD
TBD
TBD
TBD
V
lX
(CK)
Differential Input Cross Point Voltage
relative to V
DD
/2 for CK, CK#
TBD
TBD
TBD
TBD
CMOS rail to rail Input Levels for RESET#
Table 106. CMOS rail to rail Input Levels for RESET#
Symbol
Parameter
Min.
Max.
Unit
Note
V
IH(AC)
_RESET
AC Input High Voltage
0.8 x V
DDQ
V
DD
V
6
V
IH(DC)
_RESET
DC Input High Voltage
0.7 x V
DDQ
V
DD
V
2
V
IL(DC)
_RESET
DC Input Low Voltage
V
SS
0.3 x V
DDQ
V
1
V
IL(AC)
_RESET
AC Input Low Voltage
V
SS
0.2 x V
DDQ
V
7
TR_RESET
Rising time
-
1.0
μs
4
t
PW
_RESET
RESET pulse width
1.0
-
μs
3,5
Note 1. After RESET# is registered Low, RESET# level shall be maintained below V
IL(DC)
_RESET during t
PW
_RESET, otherwise, SDRAM
may not be reset.
Note 2. Once RESET# is registered High, RESET# level must be maintained above V
IH(DC)
_RESET, otherwise, SDRAM operation will not
be guaranteed until it is reset asserting RESET# signal Low.
Note 3. RESET is destructive to data contents.
Note 4. No slope reversal (ringback) requirement during its level transition from Low to High.
Note 5. This definition is applied only “Reset Procedure at Power Stable”.
Note 6. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.
Note 7. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019