Datasheet
Mode Register MR2
Table 10. MR2 Definition
BG0
BA1
BA0
RAS#
/A16
CAS#
/A15
WE#/
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
0
0
0
0
0
*1
Write
CRC
R
TT_WR
0
*1
LPASR
CWL
0
*1
0
*1
0
*1
Note 1. Reserved for future use and must be programmed to 0 during MRS.
Note 2. The 2 t
CK
Write Preamble is valid for DDR4-2400/2666 Speed Grade. For the 2
nd
Set of t
CK
Write Preamble, no additional CWL is
needed.
CAS Write Latency
CAS WRITE latency (CWL) is defined by MR2[5:3] as shown in the MR2 Register Definition table. CWL is
the delay, in clock cycles, between the internal Write command and the availability of the first bit of input data.
The device does not support any half-clock latencies. The overall Write latency (WL) is defined as additive
latency (AL) + parity latency (PL) + CAS write latency (CWL): WL = AL +PL + CWL.
Low-Power Auto Self Refresh
Low-power auto self refresh (LPASR) is supported in the device. Applications requiring Self Refresh operation
over different temperature ranges can use this feature to optimize the IDD6 current for a given temperature
range as specified in the MR2 Register Definition table.
Dynamic ODT
In certain applications and to further enhance signal integrity on the data bus, it is desirable to change the
termination strength of the device without issuing an MRS command. This may be done by configuring the
dynamic ODT (R
TT_WR
) settings in MR2[11:9]. In write leveling mode, only R
TT_NOM
is available.
Write Cyclic Redundancy Check Data Bus
The write cyclic redundancy check (CRC) data bus feature during writes has been added to the device.
When enabled via the mode register, the data transfer size goes from the normal 8-bit (BL8) frame to a larger
10-bit UI frame, and the extra two UIs are used for the CRC information.
A12
Write CRC
A11
A10
A9
R
TT_WR
0
Disable
0
0
0
R
TT(WR)
disabled
(Write does not affect R
TT
value)
1
Enable
0
0
1
RZQ/2
0
1
0
RZQ/1
0
1
1
Hi-Z
1
0
0
RZQ/3
A5
A4
A3
CWL
Operating Data Rate in MT/s
for 1 t
CK
Write Preamble
Operating Data Rate in MT/s
for 2 t
CK
Write Preamble
*2
1
st
Set
2
nd
Set
1
st
Set
2
nd
Set
0
0
0
9
1600
-
-
-
0
0
1
10
1866
-
-
-
0
1
0
11
2133
1600
-
-
0
1
1
12
2400
1866
-
-
1
0
0
14
2666
2133
2400
-
1
0
1
16
-
2400
2666
2400
1
1
0
18
-
2666
-
2666
A7
A6
Low Power Auto Self Refresh (LPASR)
0
0
Manual Mode - Normal Operating Temperature Range (T
C
: -40°C ~ 85°C)
0
1
Manual Mode - Reduced Operating Temperature Range (T
C
: -40°C ~ 45°C)
1
0
Manual Mode - Extended Operating Temperature Range (T
C
: -40°C ~ 95°C)
1
1
ASR Mode (Auto Self Refresh)
AS4C256M16D4
Confidential
- 19 of 201 -
Rev.1.0 Aug.2019