Datasheet

Note 19. DRAM DBI mode is enabled.
Note 20. tQSL describes the instantaneous differential output low pulse width on DQS - DQS#, as measured from on falling edge to the
next consecutive rising edge.
Note 21. tQSH describes the instantaneous differential output high pulse width on DQS – DQS#, as measured from on falling edge to the
next consecutive rising edge.
Note 22. There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI.
Note 23. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
Note 24. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
Note 25. Total jitter includes the sum of deterministic and random jitter terms for a specified BER. BER target and measurement method
are TBD.
Note 26. The deterministic jitter component out of the total jitter. This parameter is characterized and guaranteed by design.
Note 27. This parameter has to be even number of clocks.
Note 28. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.
Note 29. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.
Note 30. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.
Note 31. After CKE is registered low, CKE signal level shall be maintained below VILDC for tCKE specification (low pulse width).
Note 32. After CKE is registered high, CKE signal level shall be maintained above VIHDC for tCKE specification (high pulse width).
Note 33. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
Note 34. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed-Bin tables.
Note 35. This parameter must keep consistency with Speed-Bin tables.
Note 36. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate. UI = tCK(avg).min/2
Note 37. Applied when DRAM is in DLL ON mode.
Note 38. Assume no jitter on input clock signals to the DRAM.
Note 39. Value is only valid for RONNOM = 34 ohms.
Note 40. 1tCK toggle mode with setting MR4 A[11] to 0.
Note 41. 2tCK toggle mode with setting MR4 A[11] to 1, which is valid for DDR4-2400/2666 speed grade.
Note 42. 1tCK mode with setting MR4 A[12] to 0.
Note 43. 2tCK mode with setting MR4 A[12] to 1, which is valid for DDR4-2400/2666 speed grade.
Note 44. The maximum read preamble is bounded by tLZ(DQS)min on the left side and tDQSCK(max) on the right side. See Clock to Data
Strobe Relationship. Boundary of DQS Low-Z occur one cycle earlier in 2tCK toggle mode which is illustrated in Read Preamble.
Note 45. DQ falling signal middle-point of transferring from High to Low to first rising edge of DQS diff-signal cross-point.
Note 46. Last falling edge of DQS diff-signal cross-point to DQ rising signal middle-point of transferring from Low to High.
Note 47. VREFDQ value must be set to either its midpoint or Vcent_DQ (midpoint) in order to capture DQ0 low level for entering PDA mode.
Note 48. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See Clock
to Data Strobe Relationship.
Note 49. Reference level of DQ output signal is specified with a midpoint as a widest part of Output signal eye which should be
approximately 0.7 x VDDQ as a center level of the static single-ended output peak-to-peak swing with a driver impedance of 34
ohms and an effective test load of 50 ohms to VTT = VDDQ.
Note 50. For MR7 commands, the minimum delay to a subsequent non-MRS command is 5nCK.
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019