Datasheet
Note 1. Start of internal write transaction is defined as follows:
- For BL8 (Fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
- For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL.
- For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL.
Note 2. A separate timing parameter will cover the delay from write to read when CRC and DM are simultaneously enabled.
Note 3. Commands requiring a locked DLL are: Read (and RAP) and synchronous ODT commands.
Note 4. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer.
Note 5. WR in clock cycles as programmed in MR0.
Note 6. tREFI depends on TOPER.
Note 7. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress,
but power-down IDD spec will not be applied until finishing those operations.
Note 8. For these parameters, the DDR4 SDRAM device supports tnPARAM[nCK]=RU{tPARAM[ns]/tCK(avg)[ns]}, which is in clock cycles
assuming all input clock jitter specifications are satisfied.
Note 9. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.
Note 10. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.
Note 11. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L.
Note 12. The max values are system dependent.
Note 13. DQ to DQS total timing per group where the total includes the sum of deterministic and random timing terms for a specified BER.
BER spec and measurement method are TBD.
Note 14. The deterministic component of the total timing. Measurement method TBD.
Note 15. DQ to DQ static offset relative to strobe per group. Measurement method TBD.
Note 16. This parameter will be characterized and guaranteed by design.
Note 17. When the device is operated with the input clock jitter, this parameter needs to be derated by the actual tJIT(per)_total of the input
clock. (Output deratings are relative to the SDRAM input clock). Example TBD.
Note 18. DRAM DBI mode is off.
tMRD_PDA
Mode Register Set command cycle time in PDA mode
max(16nCK
, 10ns)
-
max(16nCK
, 10ns)
-
ns
tMOD_PDA
Mode Register Set command update delay in PDA mode
t
MOD
t
MOD
ns
ODT Timing
tAONAS
Asynchronous RTT turn-on delay (Power-Down with DLL
frozen)
1.0
9.0
1.0
9.0
ns
tAOFAS
Asynchronous RTT turn-off delay (Power-Down with DLL
frozen)
1.0
9.0
1.0
9.0
ns
tADC
RTT dynamic change skew
0.3
0.7
0.3
0.7
t
CK
Write Leveling Timing
tWLMRD
12
First DQS/DQS# rising edge after write leveling mode is
programmed
40
-
40
-
t
CK
tWLDQSEN
12
DQS/DQS# delay after write leveling mode is programmed
25
-
25
-
t
CK
tWLS
Write leveling setup time from rising CK, CK# crossing to
rising DQS/DQS# crossing
0.13
-
0.13
-
t
CK
tWLH
Write leveling hold time from rising DQS/DQS# crossing to
rising CK, CK# crossing
0.13
-
0.13
-
t
CK
tWLO
Write leveling output delay
0
9.5
0
9.5
ns
tWLOE
Write leveling output error
0
2
0
2
ns
CA Parity Timing
tPAR_UNKNOWN
Commands not guaranteed to be executed during this time
-
PL
-
PL
t
CK
tPAR_ALERT_ON
Delay from errant command to ALERT# assertion
-
PL + 6ns
-
PL + 6ns
t
CK
tPAR_ALERT_PW
Pulse width of ALERT# signal when asserted
72
144
80
160
t
CK
tPAR_ALERT_RSP
Time from when Alert is asserted till controller must start
providing DES commands in Persistent CA parity mode
-
64
-
71
t
CK
PL
Parity Latency
5
t
CK
CRC Error Reporting
tCRC_ALERT
CRC error to ALERT# latency
3
13
3
13
ns
tCRC_ALERT_PW
CRC ALERT# pulse width
6
10
6
10
t
CK
Geardown timing
tXPR_GEAR
Exit Reset from CKE High to a valid MRS Gear Down (T2/ Reset)
-
-
TBD
-
tXS_GEAR
CKE High Assert to Gear Down Enable time(T2/CKE)
-
-
TBD
-
tSYNC_GEAR
27
MRS command to Sync pulse time(T3)
-
-
TBD
-
tCMD_GEAR
27
Sync pulse to First valid command(T4)
-
-
TBD
-
tGEAR_setup
Geardown setup time
2
-
2
-
t
CK
tGEAR_hold
Geardown hold time
2
-
2
-
t
CK
tREFI
tRFC1 (min)
34
4Gb
260
-
260
-
ns
tRFC2 (min)
34
4Gb
160
-
160
-
ns
tRFC4 (min)
34
4Gb
110
-
110
-
ns
t
REFI
Average periodic refresh interval
7.8
-
7.8
-
μs
85°C ≤ T
CASE
≤ 95°C
3.9
-
3.9
-
μs
-40°C ≤ T
CASE
≤ 85°C
AS4C256M16D4
Confidential
- 184 of 201 -
Rev.1.0 Aug.2019