Datasheet
tQSL
20,39
DQS, DQS# differential output low time
0.4
-
0.4
-
t
CK
tWPRE
42
DQS, DQS# differential Write Preamble (1 clock preamble)
0.9
-
0.9
-
t
CK
tWPRE2
43
DQS, DQS# differential Write Preamble (2 clock preamble)
1.8
-
1.8
-
t
CK
tWPST
DQS, DQS# differential Write Postamble
0.33
-
0.33
-
t
CK
tLZ(DQS)
39
DQS, DQS# low impedance time (Referenced from RL-1)
-330
175
-310
170
ps
tHZ(DQS)
39
DQS, DQS# high impedance time (Referenced from
RL+BL/2)
-
175
-
170
ps
tDQSL
DQS, DQS# differential input low pulse width
0.46
0.54
0.46
0.54
t
CK
tDQSH
DQS, DQS# differential input high pulse width
0.46
0.54
0.46
0.54
t
CK
tDQSS
42
DQS, DQS# rising edge to CK, CK# rising edge
(1 clock preamble)
-0.27
0.27
-0.27
0.27
t
CK
tDQSS2
43
DQS, DQS# rising edge to CK, CK# rising edge
(2 clock preamble)
TBD
TBD
TBD
TBD
t
CK
tDSS
DQS, DQS# falling edge setup time to CK, CK# rising edge
0.18
-
0.18
-
t
CK
tDSH
DQS, DQS# falling edge hold time from CK, CK# rising
edge
0.18
-
0.18
-
t
CK
tDQSCK(DLL On)
37,38,39
DQS, DQS# rising edge output timing location from
rising CK, CK# with DLL On mode
-175
175
-170
170
ps
tDQSCKI(DLL On)
37,38,39
DQS, DQS# rising edge output variance window per DRAM
-
290
-
270
ps
Calibration Timing
tZQinit
Power-up and Reset calibration time
1024
-
1024
-
t
CK
tZQoper
Normal operation Full calibration time
512
-
512
-
t
CK
tZQCS
Normal operation Short calibration time
128
-
128
-
t
CK
Reset/Self Refresh Timing
tXPR
Exit Reset from CKE HIGH to a valid command
max(5nCK,
tRFC(min) +
10ns)
-
max(5nCK,
tRFC(min) +
10ns)
-
t
CK
tXS
Exit Self Refresh to commands not requiring a locked DLL
tRFC(min) +
10ns
-
tRFC(min) +
10ns
-
t
CK
tXS_ABORT(min)
SRX to commands not requiring a locked DLL in Self
Refresh ABORT
tRFC4(min) +
10ns
-
tRFC4(min) +
10ns
-
t
CK
tXS_FAST(min)
Exit Self Refresh to ZQCL,ZQCS and MRS (CL, CWL, WR,
RTP and Gear Down)
tRFC4(min) +
10ns
-
tRFC4(min) +
10ns
-
t
CK
tXSDLL
Exit Self Refresh to commands requiring a locked DLL
tDLLK(min)
-
tDLLK(min)
-
t
CK
tCKESR
Minimum CKE low width for Self refresh entry to exit timing
tCKE(min) +
1nCK
-
tCKE(min) +
1nCK
-
t
CK
tCKESR_PAR
Minimum CKE low width for Self refresh entry to exit timing
with CA Parity enabled
tCKE(min) +
1nCK + PL
-
tCKE(min) +
1nCK + PL
-
t
CK
tCKSRE
Valid Clock Requirement after Self Refresh Entry (SRE) or
Power-Down Entry (PDE)
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
t
CK
tCKSRE_PAR
Valid Clock Requirement after Self Refresh Entry (SRE) or
Power-Down when CA Parity is enabled
max(5nCK,
10ns) + PL
-
max(5nCK,
10ns) + PL
-
t
CK
tCKSRX
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
t
CK
Power Down Timing
tXP
Exit Power Down with DLL on to any valid command; Exit
Precharge Power Down with DLL frozen to commands not
requiring a locked DLL
max(4nCK,
6ns)
-
max(4nCK,
6ns)
-
t
CK
tCKE
31,32
CKE minimum pulse width
max(3nCK,
5ns)
-
max(3nCK,
5ns)
-
t
CK
tCPDED
Command pass disable delay
4
-
4
-
t
CK
tPD
6
Power Down Entry to Exit Timing
t
CKE(min)
9 x t
REFI
t
CKE(min)
9 x t
REFI
t
CK
tACTPDEN
7
Timing of ACT command to Power Down entry
2
-
2
-
t
CK
tPRPDEN
7
Timing of PRE or PREA command to Power Down entry
2
-
2
-
t
CK
tRDPDEN
Timing of RD/RDA command to Power Down entry
RL
+ 4
+ 1
-
RL
+ 4
+ 1
-
t
CK
tWRPDEN
4
Timing of WR command to Power Down entry (BL8OTF,
BL8MRS, BC4OTF)
WL + 4 +
(tWR/tCK(avg))
-
WL + 4 +
(tWR/tCK(avg))
-
t
CK
tWRAPDEN
5
Timing of WRA command to Power Down entry (BL8OTF,
BL8MRS, BC4OTF)
WL + 4 +
WR + 1
-
WL + 4 +
WR + 1
-
t
CK
tWRPBC4DEN
4
Timing of WR command to Power Down entry (BC4MRS)
WL + 2 +
(tWR/tCK(avg))
-
WL + 2 +
(tWR/tCK(avg))
-
t
CK
tWRAPBC4DEN
5
Timing of WRA command to Power Down entry (BC4MRS)
WL + 2 +
WR + 1
-
WL + 2 +
WR + 1
-
t
CK
tREFPDEN
7
Timing of REF command to Power Down entry
2
-
2
-
t
CK
tMRSPDEN
Timing of MRS command to Power Down entry
tMOD(min)
-
tMOD(min)
-
t
CK
PDA Timing
AS4C256M16D4
Confidential
- 183 of 201 -
Rev.1.0 Aug.2019