Datasheet

tERR(18per)
Cumulative error across 18 cycles
-124
124
-112
112
ps
tERR(nper)
Cumulative error across n =13, 14 . . . 49, 50 cycles
tERR(nper)min = ((1 + 0.68ln(n)) x tJIT(per)_total min)
t
ERR(nper)max
= ((1 + 0.68
ln(n
)) x t
JIT(per)_total max
)
ps
tIS(base)
Command and Address setup time to CK, CK# referenced
to VIH(AC)/VIL(AC) levels
62
-
55
-
ps
tIS(V
REF
)
Command and Address setup time to CK, CK# referenced
to V
REF
levels
162
-
145
-
ps
tIH(base)
Command and Address hold time to CK, CK# referenced to
VIH(AC)/VIL(AC) levels
87
-
80
-
ps
tIH(V
REF
)
Command and Address hold time to CK, CK# referenced to
V
REF
levels
162
-
145
-
ps
tIPW
Control and Address Input pulse width for each input
410
-
385
-
ps
Command and Address Timing
tCCD_L
34
CAS# to CAS# command delay for same bank group
max(5nCK,
5ns)
-
max(5nCK,
5ns)
-
t
CK
tCCD_S
34
CAS# to CAS# command delay for different bank group
4
-
4
-
t
CK
tRRD_S(2K)
34
Activate to Activate Command delay to different bank group
for 2KB page size
max(4nCK,
5.3ns)
-
max(4nCK,
5.3ns)
-
t
CK
tRRD_L(2K)
34
Activate to Activate Command delay to same bank group for
2KB page size
max(4nCK,
6.4ns)
-
max(4nCK,
6.4ns)
-
t
CK
tFAW_2K
34
Four activate window for 2KB page size
max(28nCK
,30ns)
-
max(28nCK
,30ns)
-
ns
tWTR_S
1,2,34
Delay from start of internal write transaction to internal
read command for different bank group
max(2nCK,
2.5ns)
-
max(2nCK,
2.5ns)
-
tWTR_L
1,34
Delay from start of internal write transaction to internal
read command for same bank group
max(4nCK,
7.5ns)
-
max(4nCK,
7.5ns)
-
tRTP
34
Internal Read Command to Precharege Command delay
max(4nCK,
7.5ns)
-
max(4nCK,
7.5ns)
-
tWR
1
WRITE recovery time
15
-
15
-
ns
tWR_CRC_DM
1,28
Write recovery time when CRC and DM are enabled
tWR +
max(5nCK,
3.75ns)
-
tWR +
max(5nCK,
3.75ns)
-
ns
tWTR_S_CRC_DM
2,29,34
delay from start of internal write transaction to internal
read command for different bank groups with both CRC
and DM enabled
tWTR_S +
max(5nCK,
3.75ns)
-
tWTR_S +
max(5nCK,
3.75ns)
-
ns
tWTR_L_CRC_DM
3,30,34
delay from start of internal write transaction to internal
read command for same bank group with both CRC
and DM enabled
tWTR_L
+max(5nCK
,3.75ns)
-
tWTR_L
+max(5nCK
,3.75ns)
-
ns
tDLLK
DLL locking time
768
-
854
-
t
CK
tMRD
Mode Register Set command cycle time
8
-
8
-
t
CK
tMOD
50
Mode Register Set command update delay
max(24nCK
,15ns)
-
max(24nCK
,15ns)
-
t
CK
tMPRR
33
Multi-Purpose Register Recovery Time
1
-
1
-
t
CK
tWR_MPR
Multi Purpose Register Write Recovery Time
tMOD(min) +
AL + PL
-
tMOD(min) +
AL + PL
-
t
CK
tDAL(min)
Auto precharge write recovery + precharge time
Programmed WR + roundup (tRP/ tCK(avg))
tCK
tPDA_S
45,47
DQ0 driven to 0 setup time to first DQS rising edge
0.5
-
0.5
-
UI
tPDA_H
46,47
DQ0 driven to 0 hold time from last DQS falling edge
0.5
-
0.5
-
UI
CS# to Command Address Latency
tCAL
CS# to Command Address Latency
max(3nCK,
3.748ns)
-
5
-
t
CK
tMRD_tCAL
Mode Register Set command cycle time in CAL mode
tMOD + tCAL
-
tMOD + tCAL
-
t
CK
tMOD_tCAL
Mode Register Set update delay in CAL mode
tMOD + tCAL
-
tMOD + tCAL
-
t
CK
DRAM Data Timing
tDQSQ
13,18,39,49
DQS, DQS# to DQ skew, per group, per access
-
0.17
-
0.18
t
CK
tQH
13,17,18,39,49
DQ output hold time per group, per access from DQS,DQS#
0.74
-
0.74
-
t
CK
tDVWd
17,18,39,49
Data Valid Window per device per UI: (tQH - tDQSQ) of each
UI on a given DRAM
0.64
-
TBD
-
UI
tDVWp
17,18,39,49
Data Valid Window per pin per UI: (tQH - tDQSQ) each UI on
a pin of a given DRAM
0.72
-
0.72
-
UI
tLZ(DQ)
39
DQ low impedance time from CK, CK#
-330
175
-310
170
ps
tHZ(DQ)
39
DQ high impedance time from CK, CK#
-
175
-
170
ps
Data Strobe Timing
tRPRE
39,40, 44
DQS, DQS# differential Read Preamble (1 clock preamble)
0.9
-
0.9
-
t
CK
tRPRE2
39,41,44
DQS, DQS# differential Read Preamble (2 clock preamble)
1.8
-
1.8
-
t
CK
tRPST
39,45
DQS, DQS# differential Read Postamble
0.33
-
0.33
-
t
CK
tQSH
21,39
DQS, DQS# differential output high time
0.4
-
0.4
-
t
CK
AS4C256M16D4
Confidential
- 182 of 201 -
Rev.1.0 Aug.2019