Datasheet
Table 92. Timing Parameters
Symbol
Parameter
DDR4-2400
DDR4-2666
Unit
Min.
Max.
Min.
Max.
tAA
Internal read command to first data
14.16
18
14.25
18
ns
tAA_DBI
Internal read command to first data with read DBI enabled
t
AA(min)
+
3 t
CK
t
AA(max)
+ 3
t
CK
t
AA(min)
+
3 t
CK
t
AA(max)
+ 3
t
CK
ns
tRCD
ACT to internal read or write delay time
14.16
-
14.25
-
ns
tRP
PRE command period
14.16
-
14.25
-
ns
tRAS
ACT to PRE command period
32
9 x t
REFI
32
9 x t
REFI
ns
tRC
ACT to ACT or REF command period
46.16
-
46.25
-
ns
Speed Bins
CWL
Normal
Read DBI
Min.
Max.
Min.
Max.
Unit
tCK(avg)
ACT to ACT or REF
command period
9
10
12
1.5
1.6
1.5
1.6
ns
9,11
11
13
1.25
<1.5
1.25
<1.5
ns
9,11
12
14
1.25
<1.5
1.25
<1.5
ns
10,12
13
15
1.071
<1.25
1.071
<1.25
ns
10,12
14
16
1.071
<1.25
1.071
<1.25
ns
11,14
15
18
0.937
<1.071
0.937
<1.071
ns
11,14
16
19
0.937
<1.071
0.937
<1.071
ns
12,16
17
20
0.833
<0.937
0.833
<0.937
ns
12,16
18
21
-
-
0.833
<0.937
ns
14,18
19
22
-
-
0.75
<0.833
ns
Clock Timing
tCK (DLL_OFF)
Minimum Clock Cycle Time (DLL off mode)
8
20
8
20
ns
tCK(avg)
35,36
Average clock period
0.833
<0.937
0.750
<0.833
ns
tCH(avg)
Average high pulse width
0.48
0.52
0.48
0.52
tCK
tCL(avg)
Average low pulse width
0.48
0.52
0.48
0.52
t
CK
t
CK(abs)
Absolute Clock Period
tCK(avg)min +
tJIT(per)min_tot
tCK(avg)max +
tJIT(per)max_tot
tCK(avg)min +
tJIT(per)min_tot
tCK(avg)max +
tJIT(per)max_tot
tCK
tCH(abs)
23
Absolute clock high pulse width
0.45
-
0.45
-
t
CK
tCL(abs)
24
Absolute clock low pulse width
0.45
-
0.45
-
tCK
JIT(per)_tot
25
Clock Period Jitter- total
-42
42
-38
38
ps
JIT(per)_dj
26
Clock Period Jitterdeterministic
-21
21
-19
19
ps
tJIT(per,lck)
Clock Period Jitter during DLL locking period
-33
33
-30
30
ps
t
JIT(cc)
Cycle to Cycle Period Jitter
-
83
-
75
ps
tJIT(cc,lck)
Cycle to Cycle Period Jitter during DLL locking period
-
67
-
60
ps
t
JIT(duty)
Duty Cycle Jitter
TBD
TBD
TBD
TBD
ps
tERR(2per)
Cumulative error across 2 cycles
-61
61
-55
55
ps
tERR(3per)
Cumulative error across 3 cycles
-73
73
-66
66
ps
tERR(4per)
Cumulative error across 4 cycles
-81
81
-73
73
ps
tERR(5per)
Cumulative error across 5 cycles
-87
87
-78
78
ps
tERR(6per)
Cumulative error across 6 cycles
-92
92
-83
83
ps
tERR(7per)
Cumulative error across 7 cycles
-97
97
-87
87
ps
tERR(8per)
Cumulative error across 8 cycles
-101
101
-91
91
ps
tERR(9per)
Cumulative error across 9 cycles
-104
104
-94
94
ps
tERR(10per)
Cumulative error across 10 cycles
-107
107
-96
96
ps
tERR(11per)
Cumulative error across 11 cycles
-110
110
-99
99
ps
tERR(12per)
Cumulative error across 12 cycles
-112
112
-101
101
ps
tERR(13per)
Cumulative error across 13 cycles
-114
114
-103
103
ps
tERR(14per)
Cumulative error across 14 cycles
-116
116
-104
104
ps
tERR(15per)
Cumulative error across 15 cycles
-118
118
-106
106
ps
tERR(16per)
Cumulative error across 16 cycles
-120
120
-108
108
ps
tERR(17per)
Cumulative error across 17 cycles
-122
122
-110
110
ps
AS4C256M16D4
Confidential
- 181 of 201 -
Rev.1.0 Aug.2019