Datasheet
Mode Register MR1
Table 9. MR1 Definition
BG0
BA1
BA0
RAS#
/A16
CAS#
/A15
WE#/
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
1
0
0
0
0
*1
Qoff
*2
0
*1
R
TT_NOM
WL
0
*1
0
*1
AL
*4
ODI
DLL
Note 1. Reserved for future use and must be programmed to 0 during MRS.
Note 2. Outputs disabled - DQs, DQSs, DQS#s.
Note 3. States reversed to “0 as Disable” with respect to DDR4.
Note 4. Additive Latency is not supported for x16 device.
DLL Enable/DLL Disable
The DLL must be enabled for normal operation and is required during power-up initialization and upon
returning to normal operation after having the DLL disabled. During normal operation (DLL enabled with
MR1[0]) the DLL is automatically disabled when entering the Self Refresh operation and is automatically re-
enabled upon exit of the Self Refresh operation. Any time the DLL is enabled and subsequently reset, t
DLLK
clock cycles must occur before a Read or Synchronous ODT command can be issued to allow time for the
internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result
in a violation of the t
DQSCK
, t
AON
, or t
AOF
parameters.
During t
DLLK
, CKE must continuously be registered High. The device does not require DLL for any Write
operation, except when R
TT_WR
is enabled and the DLL is required for proper ODT operation.
The direct ODT feature is not supported during DLL off mode. The ODT resistors must be disabled by
continuously registering the ODT pin Low and/or by programming the R
TT_NOM
bits MR1[10:8] = 000 via an
MRS command during DLL off mode.
The dynamic ODT feature is not supported in DLL off mode; to disable dynamic ODT externally, use the
MRS command to set R
TT_WR
, MR2[11:9] = 00.
Output Driver Impedance Control
The output driver impedance of the device is selected by MR1[2:1].
A12
Qoff
A7
Write Leveling Enable
A0
DLL Enable
A2
A1
Output Driver Impedance Control
0
Output buffer enabled
0
Disable
0
Disable
*3
0
0
RZQ/7
1
Output buffer disabled
1
Enable
1
Enable
0
1
RZQ/5
1
0
Reserved
1
1
Reserved
A10
A9
A8
R
TT_NOM
A4
A3
Additive Latency
0
0
0
R
TT_NOM
Disable
0
0
0(AL disabled)
0
0
1
RZQ/4
0
1
CL-1
0
1
0
RZQ/2
1
0
CL-2
0
1
1
RZQ/6
1
1
Reserved
1
0
0
RZQ/1
1
0
1
RZQ/5
1
1
0
RZQ/3
1
1
1
RZQ/7
AS4C256M16D4
Confidential
- 17 of 201 -
Rev.1.0 Aug.2019