Datasheet

IDD6E
Self-Refresh Current: Extended Temperature Range
T
CASE
: 0 - 95°C; Low Power Auto Self Refresh (LP ASR): Extended
4
; CKE: Low; External clock: Off; CK and CK#:
LOW; CL: see IDD timing table; BL: 8
1
; AL: 0; CS#, Command, Address, Bank Group Address, Bank Address, Data
IO: High; DM#:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT:
Enabled in Mode Registers
2
; ODT Signal: MID-LEVEL
IPP6E
Self Refresh IPP Current: Extended Temperature Range
Same condition with IDD6E
IDD6R
Self-Refresh Current: Reduced Temperature Range
T
CASE
: 0 - 45°C; Low Power Auto Self Refresh (LP ASR) : Reduced
4
; CKE: Low; External clock: Off; CK and CK#:
LOW; CL: see IDD timing table; BL: 8
1
; AL: 0; CS#, Command, Address, Bank Group Address, Bank Address, Data
IO: High; DM#:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT:
Enabled in Mode Registers
2
; ODT Signal: MID-LEVEL
IPP6R
Self Refresh IPP Current: Reduced Temperature Range
Same condition with IDD6R
IDD6A
Auto Self-Refresh Current
T
CASE
: 0 - 95°C; Low Power Auto Self Refresh (LP ASR) : Auto
4
; CKE: Low; External clock: Off; CK and CK#: LOW;
CL: see IDD timing table; BL: 8
1
; AL: 0; CS#, Command, Address, Bank Group Address, Bank Address, Data IO:
High; DM#: stable at 1; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode
Registers
2
; ODT Signal: MID-LEVEL
IPP6A
Auto Self-Refresh IPP Current
Same condition with IDD6A
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see IDD timing table; BL: 8
1
; AL: CL-1;
CS#: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially
toggling according to IDD Loop table; Data IO: read data bursts with different data between one burst and the next
one according to IDD Loop table; DM#: stable at 1; Bank Activity: two times interleaved cycling through banks (0,
1, ...7) with different addressing, see IDD Loop table; Output Buffer and RTT: Enabled in Mode Registers
2
; ODT
Signal: stable at 0; Pattern Details: see IDD Loop table
IPP7
Operating Bank Interleave Read IPP Current
Same condition with IDD7
Note 1. Burst Length: BL8 fixed by MRS: set MR0 A[1:0] =00.
Note 2. Output Buffer Enable:
- set MR1 A12 = 0: Qoff = Output buffer enabled
- set MR1 A [2:1] = 00: Output Driver Impedance Control = RZQ/7
R
TT_NOM
enable: set MR1 A [10:8] = 011: R
TT_NOM
= RZQ/6
R
TT_WR
enable: set MR2 A [10:9] = 01: R
TT_WR
= RZQ/2
R
TT_PARK
disable: set MR5 A [8:6] = 000
Note 3. CAL Enabled: set MR4 A [8:6] = 001: 1600 MT/s, 010: 1866MT/s, 2133MT/s, 011: 2400MT/s, 2666MT/s
Gear Down mode enabled: set MR3 A3 = 1:1/4 Rate
DLL disabled: set MR1 A0 = 0
CA parity enabled: set MR5 A [2:0] = 001:1600MT/s, 1866MT/s, 2133MT/s, 010: 2400MT/s, 2666MT/s
Read DBI enabled: set MR5 A12 = 1
Write DBI enabled: set: MR5 A11 = 1
Note 4. Low Power Array Self Refresh (LP ASR)
- set MR2 A [7:6] = 00: Normal
- set MR2 A [7:6] = 01: Reduced Temperature range
- set MR2 A [7:6] = 10: Extended Temperature range
- set MR2 A [7:6] = 11: Auto Self Refresh
Note 5. I
DD2NG
should be measured after sync pulse (NOP) input.
Note 6. AL is not supported for x16 device.
AS4C256M16D4
Confidential
- 169 of 201 -
Rev.1.0 Aug.2019