Datasheet

IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see IDD timing Table; BL: 8
1
; AL: 0; CS#: stable at 1; Command, Address,
Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM#: stable at 1; Bank Activity: all banks
open; Output Buffer and RTT: Enabled in Mode Registers
2
; ODT Signal: stable at 0
IPP3P
Active Power-Down IPP Current
Same condition with IDD3P
IDD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see IDD timing table; BL: 8
2
; AL: 0; CS#: High between RD; Command,
Address, Bank Group Address, Bank Address Inputs: partially toggling according to IDD Loop table; Data IO:
seamless read data burst with different data between one burst and the next one according to IDD Loop table;
DM#: stable at 1; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see IDD Loop
table); Output Buffer and RTT: Enabled in Mode Registers
2
; ODT Signal: stable at 0; Pattern Details: see IDD Loop
table
IDD4RA
Operating Burst Read Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4R
IDD4RB
Operating Burst Read Current with Read DBI
Read DBI enabled
3
, Other conditions: see IDD4R
IPP4R
Operating Burst Read IPP Current
Same condition with IDD4R
IDDQ4R
(Optional)
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
IDDQ4RB
(Optional)
Operating Burst Read IDDQ Current with Read DBI
Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see IDD timing table; BL: 8
1
; AL: 0; CS#: High between WR; Command,
Address, Bank Group Address, Bank Address Inputs: partially toggling according to IDD Loop table; Data IO:
seamless write data burst with different data between one burst and the next one according to IDD Loop table;
DM#: stable at 1; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see IDD Loop
table); Output Buffer and RTT: Enabled in Mode Registers
2
; ODT Signal: stable at HIGH; Pattern Details: see IDD
Loop table
IDD4WA
Operating Burst Write Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD4W
IDD4WB
Operating Burst Write Current with Write DBI
Write DBI enabled
3
, Other conditions: see IDD4W
IDD4WC
Operating Burst Write Current with Write CRC
Write CRC enabled
3
, Other conditions: see IDD4W
IDD4W_p
ar
Operating Burst Write Current with CA Parity
CA Parity enabled
3
, Other conditions: see IDD4W
IPP4W
Operating Burst Write IPP Current
Same condition with IDD4W
IDD5B
Burst Refresh Current (1X REF)
CKE: High; External clock: On; tCK, CL, nRFC: see IDD timing table; BL: 8
1
; AL: 0; CS#: High between REF;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to IDD Loop table;
Data IO: VDDQ; DM#: stable at 1; Bank Activity: REF command every nRFC (see IDD Loop table); Output Buffer
and RTT: Enabled in Mode Registers
2
; ODT Signal: stable at 0; Pattern Details: see IDD Loop table
IPP5B
Burst Refresh Write IPP Current (1X REF)
Same condition with IDD5B
IDD5F2
Burst Refresh Current (2X REF)
tRFC=tRFC_x2, Other conditions: see IDD5B
IPP5F2
Burst Refresh Write IPP Current (2X REF)
Same condition with IDD5F2
IDD5F4
Burst Refresh Current (4X REF)
tRFC=tRFC_x4, Other conditions: see IDD5B
IPP5F4
Burst Refresh Write IPP Current (4X REF)
Same condition with IDD5F4
IDD6N
Self Refresh Current: Normal Temperature Range
T
CASE
: 0 - 85°C; Low Power Auto Self Refresh (LP ASR) : Normal
4
; CKE: Low; External clock: Off; CK and CK#:
LOW; CL: see IDD timing table; BL: 8
1
; AL: 0; CS#, Command, Address, Bank Group Address, Bank Address, Data
IO: High; DM#: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode
Registers
2
; ODT Signal: MID-LEVEL
IPP6N
Self Refresh IPP Current: Normal Temperature Range
Same condition with IDD6N
AS4C256M16D4
Confidential
- 168 of 201 -
Rev.1.0 Aug.2019