Datasheet

Table 81. Basic IDD, IPP and IDDQ Measurement Conditions
Symbol
Description
IDD0
Operating One Bank Active-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see IDD timing table; BL: 8
1
; AL: 0; CS#: High between ACT
and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to IDD Loop
table; Data IO: VDDQ; DM#: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see
IDD Loop table); Output Buffer and RTT: Enabled in Mode Registers
2
; ODT Signal: stable at 0; Pattern Details: see
IDD Loop table
IDD0A
Operating One Bank Active-Precharge Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD0
IPP0
Operating One Bank Active-Precharge IPP Current
Same condition with IDD0
IDD1
Operating One Bank Active-Read-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see IDD timing table; BL: 8
1
; AL: 0; CS#: High
between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially
toggling according to IDD Loop table; DM#: stable at 1; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... (see IDD Loop table); Output Buffer and RTT: Enabled in Mode Registers
2
; ODT Signal: stable at 0;
Pattern Details: see IDD Loop table
IDD1A
Operating One Bank Active-Read-Precharge Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD1
IPP1
Operating One Bank Active-Read-Precharge IPP Current
Same condition with IDD1
IDD2N
Precharge Standby Current (AL=0)
CKE: High; External clock: On; tCK, CL: see IDD timing table; BL: 8
1
; AL: 0; CS#: stable at 1; Command, Address,
Bank Group Address, Bank Address Inputs: partially toggling according to IDD Loop table; Data IO: VDDQ; DM#:
stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
2
; ODT Signal: stable
at 0; Pattern Details: see IDD Loop table
IDD2NA
Precharge Standby Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD2N
IPP2N
Precharge Standby IPP Current
Same condition with IDD2N
IDD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see IDD timing table; BL: 8
1
; AL: 0; CS#: stable at 1; Command, Address,
Bank Group Address, Bank Address Inputs: partially toggling according to IDD Loop table; Data IO: VSSQ; DM#:
stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
2
; ODT Signal:
toggling according to IDD Loop table; Pattern Details: see to IDD Loop table
IDDQ2NT
(Optional)
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
IDD2NL
Precharge Standby Current with CAL enabled
Same definition like for IDD2N, CAL enabled
3
IDD2NG
Precharge Standby Current with Gear Down mode enabled
Same definition like for IDD2N, Gear Down mode enabled
3,5
IDD2ND
Precharge Standby Current with DLL disabled
Same definition like for IDD2N, DLL disabled
3
IDD2N_par
Precharge Standby Current with CA parity enabled
Same definition like for IDD2N, CA parity enabled
3
IDD2P
Precharge Power-Down Current
CKE: Low; External clock: On; tCK, CL: see IDD timing table; BL: 8
1
; AL: 0; CS#: stable at 1; Command, Address,
Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM#: stable at 1; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registers
2
; ODT Signal: stable at 0
IPP2P
Precharge Power-Down IPP Current
Same condition with IDD2P
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see IDD timing table; BL: 8
1
; AL: 0; CS#: stable at 1; Command, Address,
Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM#: stable at 1;Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registers
2
; ODT Signal: stable at 0
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see IDD timing table; BL: 8
1
; AL: 0; CS#: stable at 1; Command, Address,
Bank Group Address, Bank Address Inputs: partially toggling according to IDD Loop table; Data IO: VDDQ; DM#:
stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers
2
; ODT Signal: stable
at 0; Pattern Details: see IDD Loop table
IDD3NA
Active Standby Current (AL=CL-1)
AL = CL-1, Other conditions: see IDD3N
IPP3N
Active Standby IPP Current
Same condition with IDD3N
AS4C256M16D4
Confidential
- 167 of 201 -
Rev.1.0 Aug.2019