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and I

DDQ

Specification Parameters and Test conditions

In this chapter, I

, I

and I

DDQ

measurement conditions such as test load and patterns are defined and setup

and test load for I

, I

and I

DDQ

measurements are also described here.

 I

currents (such as I

DD0

, I

DD0A

, I

DD1

, I

DD1A

, I

DD2N

, I

DD2NA

, I

DD2NL

, I

DD2NT

, I

DD2P

, I

DD2Q

, I

DD3N

, I

DD3NA

, I

DD3P

, I

DD4R

DD4RA

, I

DD4W

, I

DD4WA

, I

DD5B

, I

DD5F2

, I

DD5F4

, I

DD6N

, I

DD6E

, I

DD6R

, I

DD6A

, I

DD7

and I

DD8

) are measured as time-

averaged currents with all V

balls of the DDR4 SDRAM under test tied together. Any I

or I

DDQ

current is

not included in I

currents.

 I

currents have the same definition as I

except that the current on the V

supply is measured.

 I

DDQ

currents (such as I

DDQ2NT

and I

DDQ4R

) are measured as time-averaged currents with all V

DDQ

balls of the

DDR4 SDRAM under test tied together. Any I

current is not included in I

DDQ

currents.

Attention: I

DDQ

values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can be

used to support correlation of simulated IO power to actual IO power. In DRAM module application, I

DDQ

cannot be measured separately since V

and V

DDQ

are using one merged-power layer in Module PCB.

For I

, I

and I

DDQ

measurements, the following definitions apply:

 “0” and “LOW” is defined as V

 V

ILAC(max)

 “1” and “HIGH” is defined as V

 V

IHAC(min)

 “MID-LEVEL” is defined as inputs are V

REF

= V

/ 2.

 Timings used for I

, I

and I

DDQ

Measurement-Loop Patterns are described Timings used for I

, I

and

DDQ

Measurement-Loop Patterns.

 Basic I

, I

and I

DDQ

Measurement Conditions are described in: Basic I

, I

and I

DDQ

Measurement

Conditions.

 Detailed I

, I

and I

DDQ

are described in table: I

DD0

, I

DD0A

and I

PP0

Measurement-Loop Pattern through I

DD7

Measurement-Loop Pattern.

 I

Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not limited to

setting

- R

= RZQ/7 (34 Ohm in MR1);

- R

TT_NOM

= RZQ/6 (40 Ohm in MR1);

- R

TT_WR

= RZQ/2 (120 Ohm in MR2);

- R

TT_PARK

= Disable;

- Qoff = 0B (Output Buffer enabled) in MR1

- CRC disabled in MR2;

- CA parity feature disabled in MR5;

- Gear down mode disabled in MR3

- Read/Write DBI disabled in MR5;

- DM disabled in MR5

 Attention: The I

, I

and I

DDQ

Measurement-Loop Patterns need to be executed at least one time before

actual I

or I

DDQ

measurement is started.

 Define D = {CS#, ACT#, RAS#, CAS#, WE#}:= {HIGH, LOW, LOW, LOW, LOW}; apply BG/BA changes

when directed.

 Define D# = {CS#, ACT#, RAS#, CAS#, WE#}:= {HIGH, HIGH, HIGH, HIGH, HIGH}; apply invert of BG/BA

changes when directed above.

AS4C256M16D4

Confidential

- 164 of 201 -

Rev.1.0 Aug.2019