Datasheet
Burst Length, Type and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is
selected via bit A3 of Mode Register MR0. The ordering of accesses within a burst is determined by the burst
length, burst type, and the starting column address as shown in the following table. The burst length is defined
by bits A0-A1 of Mode Register MR0. Burst length options include fixed BC4, fixed BL8, and ‘on the fly’ which
allows BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC#.
Table 8. Burst Type and Burst Order
Burst Length
Read/Write
Starting Column Address
Burst type = Sequential
(decimal) A3=0
burst type = Interleaved
(decimal) A3=1
Note
A2
A1
A0
4 Chop
Read
0
0
0
0, 1, 2, 3, T, T, T, T
0, 1, 2, 3, T, T, T, T
1, 2, 3
0
0
1
1, 2, 3, 0, T, T, T, T
1, 0, 3, 2, T, T, T, T
0
1
0
2, 3, 0, 1, T, T, T, T
2, 3, 0, 1, T, T, T, T
0
1
1
3, 0, 1, 2, T, T, T, T
3, 2, 1, 0, T, T, T, T
1
0
0
4, 5, 6, 7, T, T, T, T
4, 5, 6, 7, T, T, T, T
1
0
1
5, 6, 7, 4, T, T, T, T
5, 4, 7, 6, T, T, T, T
1
1
0
6, 7, 4, 5, T, T, T, T
6, 7, 4, 5, T, T, T, T
1
1
1
7, 4, 5, 6, T, T, T, T
7, 6, 5, 4, T, T, T, T
Write
0
V
V
0, 1, 2, 3, X, X, X, X
0, 1, 2, 3, X, X, X, X
1, 2, 4,
5
1
V
V
4, 5, 6, 7, X, X, X, X
4, 5, 6, 7, X, X, X, X
8
Read
0
0
0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
2
0
0
1
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
0
1
0
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
0
1
1
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
1
0
0
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1
0
1
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
1
1
0
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
1
1
1
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Write
V
V
V
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
2, 4
Notes:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the BL8 mode.
This means that the starting point for t
WR
and t
WTR
will be pulled in by two clocks. In case of burst length being selected on-the-fly via
A12/BC#, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly
control, the starting point for t
WR
and t
WTR
will not be pulled in by two clocks.
2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Don’t Care.
Write Recovery (WR)/Read-to-Precharge (RTP)
The programmed write recovery (WR) value is used for the auto precharge feature along with t
RP
to determine
t
DAL
. WR for auto precharge (MIN) in clock cycles is calculated by dividing t
WR
(in ns) by t
CK
(in ns) and rounding
to the next integer:
The WR value must be programmed to be equal to or larger than t
WR
(MIN). When both DM and write CRC
are enabled in the mode register, the device calculates CRC before sending the write data into the array; t
WR
values will change when enabled. If there is a CRC error, the device blocks the Write operation and discards
the data.
Internal Read-to-Precharge (RTP) command delay for auto precharge (MIN) in clock cycles is calculated by
dividing t
RTP
(in ns) by t
CK
(in ns) and rounding to the next integer:
The RTP value in the mode register must be programmed to be equal to or larger than RTP (MIN). The
programmed RTP value is used with t
RP
to determine the ACT timing to the same bank.
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019