Datasheet

ODT Timing Definitions
Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined below
DUT
CK, CK#
DQ, DM#
DQS, DQS#
VSSQ
VDDQ
Rterm=50ohm
Timing Reference Point
VTT = VSSQ
Figure 173. ODT Timing Reference Load
ODT Timing Definitions
Definitions for t
ADC
, t
AONAS
and t
AOFAS
are provided in the table and measurement reference settings are
provided in the subsequent. The t
ADC
for the Dynamic ODT case and Read Disable ODT cases are
represented by t
ADC
of Direct ODT Control case.
Table 67. ODT Timing Definitions
Table 68. Reference Settings for ODT Timing Measurements
Note 1. MR setting is as follows.
- MR1 A10=1, A9=1, A8=1 (R
TT_NOM
_Setting)
- MR5 A8=0, A7=0, A6=0 (R
TT_PARK
Setting)
- MR2 A11=0, A10=1, A9=1 (R
TT_WR
Setting)
Note 2. ODT state change is controlled by ODT pin.
Note 3. ODT state change is controlled by Write Command.
Symbol
Begin Point Definition
End Point Definition
t
ADC
Rising edge of CK,CK# defined by the end point of DODTLoff
Extrapolated point at V
RTT_NOM
Rising edge of CK,CK# defined by the end point of DODTLon
Extrapolated point at V
SSQ
Rising edge of CK,CK# defined by the end point of ODTLcnw
Extrapolated point at V
RTT_NOM
Rising edge of CK,CK# defined by the end point of ODTLcwn4 or ODTLcwn8
Extrapolated point at V
SSQ
t
AONAS
Rising edge of CK,CK# with ODT being first registered high
Extrapolated point at V
SSQ
t
AOFAS
Rising edge of CK,CK# with ODT being first registered low
Extrapolated point at V
RTT_NOM
Measured Parameter
R
TT_PARK
R
TT_NOM
R
TT_WR
Vsw1
Vsw2
Note
t
ADC
Disable
RZQ/7
-
0.20V
0.40V
1,2
-
RZQ/7
Hi-Z
0.20V
0.40V
1,3
t
AONAS
Disable
RZQ/7
-
0.20V
0.40V
1,2
t
AOFAS
Disable
RZQ/7
-
0.20V
0.40V
1,2
AS4C256M16D4
Confidential
- 156 of 201 -
Rev.1.0 Aug.2019