Datasheet

ODT buffer disabled mode for Power down
DRAM does not provide R
TT_NOM
termination during power down when ODT input buffer deactivation mode is
enabled in MR5 bit A5. To account for DRAM internal delay on CKE line to disable the ODT buffer and block
the sampled output, the host controller must continuously drive ODT to either low or high when entering power
down (from tDODToff+1 prior to CKE low till t
CPDED
after CKE low). The ODT signal may be floating after
t
CPDEDmin
has expired. In this mode, R
TT_NOM
termination corresponding to sampled ODT at the input after CKE
is first registered low (and t
ANPD
before that) may be either R
TT_NOM
or R
TT_PARK
. t
ANPD
is equal to (WL-1) and is
counted backwards from PDE.
CK#
CK
CKE
ODT
t
CPDED
(min) +
t
ADC
(max)
t
ADC
(min)
t
DODToff+1
t
CPDED
(min)
diff
Floating
R
TT_PARK
R
TT_NOM
DODTLoff
R
TT_NOM
DRAM_RTT_async
(DLL disabled)
DRAM_RTT_sync
(DLL enabled)
R
TT_PARK
t
AONAS
(min)
t
CPDED
(min) +
t
AOFAS
(max)
Figure 171. ODT timing for power down entry with ODT buffer disable mode
When exit from power down, along with CKE being registered high, ODT input signal must be re-driven and
maintained low until t
XP
is met.
CK#
CK
CKE
ODT_A
(DLL enabled)
t
ADC
(max)
t
ADC
(min)
t
XP
diff
DODTLon
ODT_B
(DLL disabled)
DRAM_RTT_A
Floating
R
TT_PARK
R
TT_NOM
Floating
R
TT_PARK
DRAM_RTT_B
R
TT_NOM
t
XP
t
AONAS
(min)
t
AONAS
(max)
Figure 172. ODT timing for power down exit with ODT buffer disable mode
AS4C256M16D4
Confidential
- 155 of 201 -
Rev.1.0 Aug.2019