Datasheet

ODT During Reads
Because the DDR4 DRAM cannot terminate with R
TT
and drive with R
ON
at the same time; R
TT
may nominally
not be enabled until the end of the postamble as shown in the example below. At cycle T25, the device turns
on the termination when it stops driving, which is determined by t
HZ
. If the DRAM stops driving early (that is,
t
HZ
is early), then t
ADC (MIN)
timing may apply. If the DRAM stops driving late (that is, t
HZ
is late), then the DRAM
complies with t
ADC (MAX)
timing.
QA0
T0 T1 T2 T4 T5 T6 T7 T8 T19 T20
T21 T22
CK#
CK
T23 T24 T25
TRANSITIONING DATA
T26 T27 T28
CMD
ODT
RL = AL + CL
RODTLoff = RL - 2 = CL + AL - 2
R
TT_PARK
t
ADC
(min)
t
ADC
(max)
DODTLon = WL - 2
A
ADDR
t
ADC
(min)
t
ADC
(max)
R
TT_NOM
t
ADC
(min)
t
ADC
(max)
R
TT_NOM
R
TT_PARK
DQs_ODT
DQS_ODT
DQSdiff
QA1 QA2 QA3
t
ADC
(min)
t
ADC
(max)+ 1nCK
QA4 QA5 QA6 QA7
DQ
RD
diff
Figure 166. Example: CL=11, PL=0; AL=CL-1=10; RL=AL+PL+CL=21; CWL=9; DODTLon=AL+CWL-2=17;
DODTLoff=AL+CWL-2=17; 1tCK preamble)
QA0
T0 T1 T2 T4 T5 T6 T7 T8 T18 T20
T21 T22
CK#
CK
T23 T24 T25
TRANSITIONING DATA
T26 T27 T28
CMD
ODT
RL = AL + CL
RODTLoff = RL - 2 = CL + AL - 3
R
TT_PARK
t
ADC
(min)
t
ADC
(max)
DODTLon = WL - 2
A
ADDR
t
ADC
(min)
t
ADC
(max)
R
TT_NOM
t
ADC
(min)
t
ADC
(max)
R
TT_NOM
DQs_ODT
DQS_ODT
DQSdiff
QA1 QA2 QA3
t
ADC
(min)
t
ADC
(max)+ 1nCK
QA4 QA5 QA6 QA7
DQ
RD
diff
Figure 167. Example: CL=11, PL=0; AL=CL-1=10; RL=AL+PL+CL=21; CWL=9; DODTLon=AL+CWL-2=17;
DODTLoff=AL+CWL-2=17; 2tCK preamble)
AS4C256M16D4
Confidential
- 151 of 201 -
Rev.1.0 Aug.2019