Datasheet
Mode Register MR0
Table 7. MR0 Definition
BG0
BA1
BA0
RAS#
/A16
CAS#
/A15
WE#/
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
*1
0
*1
WR & RTP*
2,3
DLL
Rst
TM
CL
BT
CL
BL
Note 1. Reserved for future use and must be programmed to 0 during MR.
Note 2. WR (write recovery for autoprecharge)min in clock cycles is calculated following rounding algorithm. The WR value in the mode
register must be programmed to be equal or larger than WRmin. The programmed WR value is used with t
RP
to determine t
DAL
.
Note 3. The table shows the encodings for Write Recovery and internal Read command to Precharge command delay. For actual Write
recovery timing, please refer to AC timing table.
CAS Latency
The CAS latency (CL) setting is defined in the MR0 Register Definition table. CAS latency is the delay, in
clock cycles, between the internal read command and the availability of the first bit of output data. The device
does not support half-clock latencies. The overall read latency (RL) is defined as additive latency (AL) + CAS
latency (CL): RL = AL + CL.
Test Mode
The normal operating mode is selected by MR0[7] and all other bits set to the desired values shown in the
MR0 Register Definition table. Programming MR0[7] to a value of 1 places the device into a DRAM
manufacturer-defined test mode to be used only by the manufacturer, not by the end user. No operations or
functionality is specified if MR0[7] = 1.
DLL Reset
The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL reset function has
been issued. After the DLL is enabled, a subsequent DLL reset should be applied. Any time the DLL reset function
is used, t
DLLK
must be met before functions requiring the DLL can be used. (For example, Read commands or
ODT synchronous operations).
A8
DLL Reset
A7
Test Mode
A3
Read Burst Type
A1
A0
BL
0
No
0
Normal
0
Sequential
0
0
8 (Fixed)
1
Yes
1
Interleave
0
1
BC4 or 8 (on the fly)
1
0
BC4 (Fixed)
1
1
Reserved
A11
A10
A9
WR
RTP
A6
A5
A4
A2
CAS Latency
0
0
0
10
5
0
0
0
0
9
0
0
1
12
6
0
0
0
1
10
0
1
0
14
7
0
0
1
0
11
0
1
1
16
8
0
0
1
1
12
1
0
0
18
9
0
1
0
0
13
1
0
1
20
10
0
1
0
1
14
Write Recovery and Read to Precharge for auto precharge
0
1
1
0
15
0
1
1
1
16
1
1
0
1
17
AS4C256M16D4
Confidential
- 15 of 201 -
Rev.1.0 Aug.2019