Datasheet

Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down
definition, these modes are:
 Any bank active with CKE high
 Refresh with CKE high
 Idle mode with CKE high
 Active power-down mode (regardless of MR1 bit A10)
 Precharge power-down mode
In synchronous ODT mode, R
TT_NOM
will be turned on DODTLon clock cycles after ODT is sampled high by a
rising clock edge and turned off DODTLoff clock cycles after ODT is registered low by a rising clock edge. The
ODT latency is tied to the Write Latency (WL = CWL + AL + PL) by: DODTLon = WL - 2; DODTLoff = WL - 2.
When operating in 2t
CK
Preamble Mode, The ODT latency must be 1 clock smaller than in 1t
CK
Preamble
Mode; DODTLon = WL - 3; DODTLoff = WL - 3. (WL = CWL+AL+PL)
ODT Latency and Posted ODT
In Synchronous ODT Mode, the Additive Latency (AL) and the Parity Latency (PL) programmed into the Mode
Register MR1 applies to ODT Latencies as shown below:
Table 64. ODT Latency
Symbol
Parameter
1 t
CK
Preamble
2 t
CK
Preamble
Unit
DODTLon
Direct ODT turn on Latency
CWL + AL + PL - 2
CWL + AL + PL - 3
t
CK
DODTLoff
Direct ODT turn off Latency
CWL + AL + PL - 2
CWL + AL + PL - 3
t
CK
RODTLoff
Read command to internal ODT turn off Latency
CL + AL + PL - 2
CL + AL + PL - 3
t
CK
RODTLon4
Read command to R
TT_PARK
turn on Latency in BC4
RODTLoff + 4
RODTLoff + 5
t
CK
RODTLon8
Read command to R
TT_PARK
turn on Latency in BC8/BL8
RODTLoff + 6
RODTLoff + 7
t
CK
ODTH4
ODT Assertion time, BC4 mode
4
5
t
CK
ODTH8
ODT Assertion time, BL8 mode
6
7
t
CK
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019