Datasheet

Soft Repair of a Fail Row Address
The following is the procedure of sPPR with WR command. Note that during the soft repair sequence, no
refresh is allowed.
1. Before entering ‘sPPR’ mode, all banks must be Precharged; DBI and CRC Modes must be disabled.
2. Enable sPPR using MR4 bit “A5=1” and wait t
MOD
.
3. Issue Guard Key as four consecutive MR0 commands each with a unique address field A[17:0]. Each MR0
command should space by tMOD. MR0 Guard Key sequence is same as hPPR.
4. Issue ACT command with the Bank and Row Fail address, Write data is used to select the individual DRAM
in the Rank for repair.
5. A WR command is issued after t
RCD
, with valid column address. The DRAM will ignore the column address
given with the WR command.
6. After WL (WL = CWL + AL + PL), All DQs of Target DRAM should be low for 4t
CK
. If high is driven to All
DQs of a DRAM consecutively for equal to or longer than first 2t
CK
, then DRAM does not conduct sPPR. If
all DQs are neither low for 4t
CK
nor high for equal to or longer than first 2t
CK
, then sPPR mode execution is
unknown.
7. Wait t
WR
for the internal repair register to be written and then issue PRE to the Bank.
8. Wait 20ns after PRE which allow DRAM to recognize repaired Row address.
9. Exit PPR with setting MR4 bit “A5=0” and wait t
MOD
.
10. One soft repair address per Bank Group is allowed before a hard repair is required. When more than one
sPPR request is made to the same BG, the most recently issued sPPR address would replace the early
issued one. In the case of conducting soft repair address in a different Bank Group, Repeat Step 2 to 9.
During a soft Repair, Refresh command is not allowed between sPPR MRS entry and exit.
Once sPPR mode is exited, to confirm if target row is repaired correctly, the host can verify the repair by
writing data into the target row and reading it back after sPPR exit with MR4 [A5=0].
DON'T CARETIME BREAK
5xt
MOD
T0 T1 Ta0 Tb0 Tc0 Tc1 Td0 Td1 Te0 Te1
Te2 Tf0
CK#
CK
BG
BA
ADDR
DQs1
CKE
Tf1 Tg0 Tg1
4nCK
CMD
WL = CWL + AL +PL
Th0
MRS0MRS4 ACT WR DES DES DES DES DES DES DES PRE
DES MRS4 DES VALID
VALIDVALID BGf BGf NA NA NA NA NA NA NA VALID
NA VALID NA VALID
VALIDVALID BAf BAf NA NA NA NA NA NA NA VALID
NA VALID NA VALID
VALID
VALID
(A13=1)
VALID VALID NA NA NA NA NA NA NA VALID
NA
VALID
(A13=0)
NA VALID
sPPR Entry sPPR Repair sPPR ExitsPPR Recognition
t
RCD
t
PGM
t
PGM
t
PGM_Exit(min)
t
PGMPST(min)
DQS, DQS#
REF/
DES
REF/
DES
REF/
DES
REF/
DES
Normal
Mode
Normal
Mode
All Banks
Precharged
and idle state
Figure 161. Fail Row Soft PPR (WR Case)
AS4C256M16D4
Confidential
- 144 of 201 -
Rev.1.0 Aug.2019