Datasheet

5xt
MOD
NOTE 1. Allow REF(1X) from PL+WL+BL/2+t
WR
+t
RP
after WR
NOTE 2. Timing diagram shows possible commands but not all shown can be issued at same time; for example if REF is issued at Te1, DES must be issued At Te2 as REF would be illegal at Te2.
Likewise, DES must be issued t
RFC
prior to PRE at Tf0. All regular timings must still be satisfied.
T0 T1 Ta0 Tb0 Tc0 Tc1 Td0 Td1 Te0 Te1
Te2 Tf0
CK#
CK
BG
BA
ADDR
CKE
Tf1 Tg0 Tg1
4nCK
CMD
Th0
MRS0MRS4 ACT WRA DES DES DES DES DES
REF/
DES
REF/
DES
PRE
REF/
DES
MRS4 DES VALID
VALIDVALID BGf BGf NA NA NA NA NA NA NA VALID
NA VALID NA VALID
VALIDVALID BAf BAf NA NA NA NA NA NA NA VALID
NA VALID NA VALID
VALID
VALID
(A13=1)
VALID VALID NA NA NA NA NA NA NA VALID
NA
VALID
(A13=0)
NA VALID
hPPR Entry hPPR Repair hPPR ExithPPR Recognition
t
RCD
t
PGM
t
PGM(min)=200ms
t
PGM_Exit(min)=15ns
t
PGMPST(min)=50us
Normal
Mode
REF/
DES
REF/
DES
REF/
DES
REF/
DES
Normal
Mode
DQs1
DQS, DQS#
All Banks
Precharged
and idle state
WL = CWL + AL +PL
t
WR+
t
RP+1nCK
DON'T CARETIME BREAK
Figure 159. Hard Fail Row Repair (WRA Case)
t
MOD
T0 T1 Ta0 Tb0 Tc0 Tc1 Td0 Td1 Te0 Te1
Te2 Tf0
CK#
CK
BG
BA
ADDR
CKE
Tf1 Tg0 Tg1
4nCK
CMD
Th0
MRS0MRS4 ACT WRA DES DES DES DES DES DES DES PRE
DES MRS4 DES VALID
VALIDVALID BGf BGf NA NA NA NA NA NA NA VALID
NA VALID NA VALID
VALIDVALID BAf BAf NA NA NA NA NA NA NA VALID
NA VALID NA VALID
VALID
VALID
(A13=1)
VALID VALID NA NA NA NA NA NA NA VALID
NA
VALID
(A13=0)
NA VALID
hPPR Entry hPPR Repair hPPR ExithPPR Recognition
t
RCD
t
PGM
t
PGM(min)=200ms
t
PGM_Exit(min)=15ns
t
PGMPST(min)=50us
Normal
Mode
REF/
DES
REF/
DES
REF/
DES
REF/
DES
Normal
Mode
DQs1
DQS, DQS#
All Banks
Precharged
and idle state
WL = CWL + AL +PL
DON'T CARETIME BREAK
Figure 160. Hard Fail Row Repair (WR Case)
Programming hPPR and sPPR support in MPR0 page2
hPPR and sPPR is optional feature of DDR4 4Gb so Host can recognize if DRAM is supporting hPPR and
sPPR or not by reading out MPR0 Page2.
MPR page2;
hard PPR is supported: [7] = 1
hard PPR is not supported: [7] = 0
soft PPR is supported: [6] = 1
soft PPR is not supported: [6] = 0
Required Timing Parameters
Repair requires additional time period to repair Hard Fail Row Address into spare Row address and the
followings are requirement timing parameters for hPPR.
Table 59. hPPR Timing Parameters
Symbol
Parameter
Min.
Max.
Unit
tPGM
hPPR Programming Time
2000
-
ms
tPGM_Exit
hPPR Exit Time
15
-
ns
AS4C256M16D4
Confidential
- 142 of 201 -
Rev.1.0 Aug.2019