Datasheet

Hard Fail Row Address Repair (WRA Case)
The following is procedure of hPPR with WRA command.
1. Before entering ‘hPPR’ mode, All banks must be Precharged; DBI and CRC Modes must be disabled.
2. Enable hPPR using MR4 bit “A13=1” and wait tMOD.
3. Issue guard Key as four consecutive MR0 commands each with a unique address field A[17:0]. Each MR0
command should space by tMOD.
4. Issue ACT command with Fail Row address.
5. After t
RCD
, Issue WRA with Valid address. DRAM will consider Valid address with WRA command as ‘Don’t
Care’.
6. After WL (WL = CWL + AL + PL), All DQs of target DRAM should be low for 4t
CK
. If high is driven to All DQs
of a DRAM consecutively for equal to or longer than 2t
CK
, then DRAM does not conduct hPPR and retains
data if REF command is properly issued; if all DQs are neither low for 4t
CK
nor high for equal to or longer
than 2t
CK
, then hPPR mode execution is unknown.
7. Wait t
PGM
to allow DRAM repair target Row Address internally and issue PRE.
8. Wait t
PGM_Exit
after PRE which allow DRAM to recognize repaired Row address.
9. Exit hPPR with setting MR4 bit “A13=0”.
10. DDR4 will accept any valid command after t
PGMPST
.
11. In more than one fail address repair case, Repeat step 2 to 9.
In addition to that, hPPR mode allows REF commands from PL + WL + BL/2 + t
WR
+ t
RP
after WRA command
during t
PGM
and t
PGMPST
for proper repair; provided multiple REF commands are issued at a rate of t
REFI
or t
REFI
/2,
however back-to-back REF commands must be separated by at least t
REFI
/4 when the DRAM is in hPPR mode.
Upon receiving REF command, DRAM performs normal Refresh operation and ensure data retention with
Refresh operations except for the 2banks containing the rows being repaired, with BA[0] don’t care. Other
command except REF during t
PGM
can cause incomplete repair so no other command except REF is allowed
during t
PGM
Once hPPR mode is exited, to confirm if target row is repaired correctly, host can verify by writing
data into the target row and reading it back after hPPR exit with MR4 [A13=0] and t
PGMPST
.
Hard Fail Row Address Repair (WR Case)
The following is procedure of hPPR PPR with WR command.
1. Before entering hPPR mode, all banks must be precharged; DBI and CRC modes must be disabled.
2. Enable hPPR using MR4 bit “A13=1” and wait t
MOD
.
3. Issue guard Key as four consecutive MR0 commands each with a unique address field A [17:0]. Each MR0
command should space by t
MOD
.
4. Issue ACT command with row address.
5. After t
RCD
, issue WR with valid address. DRAM consider the valid address with WR command as ‘Don’t
Care’.
6. After WL (WL = CWL + AL + PL), All DQs of target DRAM should be low for 4t
CK
. If high is driven to All DQs
of a DRAM consecutively for equal to or longer than first 2t
CK
, then DRAM does not conduct hPPR and
retains data if REF command is properly issued; if all DQs are neither low for 4t
CK
nor high for equal to or
longer than first 2t
CK
, then hPPR mode execution is unknown.
7. Wait t
PGM
to allow DRAM repair target Row Address internally and issue PRE.
8. Wait t
PGM_Exit
after PRE which allow DRAM to recognize repaired Row address.
9. Exit hPPR with setting MR4 bit “A13=0”.
10. DDR4 will accept any valid command after t
PGMPST
.
11. In more than one fail address repair case, Repeat step 2 to10.
In this sequence, Refresh command is not allowed between hPPR MRS entry and exit.
Once hPPR mode is exited, to confirm if target row is repaired correctly, host can verify by writing data into the
target row and reading it back after hPPR exit with MR4 [A13=0] and t
PGMPST
.
AS4C256M16D4
Confidential
- 141 of 201 -
Rev.1.0 Aug.2019