Datasheet

Post Package Repair (hPPR)
DDR4 supports Fail Row address repair as optional feature for 4Gb. Supporting hPPR is identified via datasheet
and SPD in Module so should refer to DRAM manufacturer’s Datasheet. PPR provides simple and easy repair
method in the system and Fail Row address can be repaired by the electrical programming of Electrical-fuse
scheme.
With hPPR, DDR4 can correct 1Row per Bank Group
Electrical-fuse cannot be switched back to un-fused states once it is programmed. The controller should prevent
unintended hPPR mode entry and repair. (i.e. Command/Address training period)
DDR4 defines two hard fail row address repair sequences and users can choose to use among those 2 command
sequences. The first command sequence uses a WRA command and ensures data retention with Refresh
operations except for the 2banks containing the rows being repaired, with BA[0] a don’t care. Second command
sequence is to use WR command and Refresh operation can’t be performed in the sequence. So, the second
command sequence doesn’t ensure data retention for target DRAM.
When hard PPR Mode is supported, entry into hPPR Mode is to be is protected through a sequential MRS guard
key to prevent unintentional hPPR programming. When soft PPR Mode, i.e. sPPR, is supported, entry into
sPPR Mode is to be protected through a sequential MRS guard key to prevent unintentional sPPR programming.
The sequential MRS guard key for hPPR mode and sPPR is the same Guard Key, i.e. hPPR/sPPR Guard Key.
The hPPR/sPPR Guard Key requires a sequence of four MR0 commands to be executed immediately after
entering hPPR mode (setting MR4 bit 13 to a “1”) or immediately after entering sPPR mode(setting MR4 bit 5
to a “1”). The hPPR/sPPR Guard Key’s sequence must be entered in the specified order as stated and shown
in the spec below. Any interruption of the hPPR/sPPR Guard Key sequence from other MR commands or non-
MR commands such as ACT, WR, RD, PRE, REF, ZQ, NOP, RFU is not allowed. Although interruption of the
hPPR/sPPR Guard Key entry is not allowed, if the hPPR/sPPR Guard Key is not entering in the required order or
is interrupted by other commands, the hPPR Mode or sPPR Mode will not execute and the offending command
terminating hPPR/sPPR Mode may or may not execute correctly; however, the offending command will not
cause the DRAM to “lock up”. Additionally, when the hPPR or sPPR entry sequence is interrupted, subsequent
ACT and WR commands will be conducted as normal DRAM commands. If a hPPR operation was prematurely
terminated, the MR4 bit 13 must be re-set “0” prior to performing another hPPR or sPPR operation. If a sPPR
operation was prematurely terminated, the MR4 bit 5 must be re-set to “0” prior to performing another sPPR or
hPPR operation. The DRAM does not provide an error indication if an incorrect hPPR/sPPR Guard Key sequence
is entered.
Table 58. hPPR and sPPR MR0 Guard Key Sequences
Guard Keys
BG1:0
(1)
BA1:0
A16:A12
A11
A10
A9
A8
A7
A6:A0
1
st
MR0
00
00
X
1
1
0
0
1
1111111
2
nd
MR0
00
00
X
0
1
1
1
1
1111111
3
rd
MR0
00
00
X
1
0
1
1
1
1111111
4
th
MR0
00
00
X
0
0
1
1
1
1111111
Note 1. BG1 is ‘Don’t Care’ in x16
Note 2. A6:A0 can be either ‘1111111’ or ‘Don’t Care’. And, it depends on vendor’s implementation. ‘1111111’ is allowed in all DDR4
density but ‘Don’t Care’ in A6:A0 is only allowed in 4Gb die DDR4 product.
Note 3. After completing hPPR and sPPR mode, MR0 must be re-programmed to pre-PPR mode state if the DRAM is to be accessed.
AS4C256M16D4
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Rev.1.0 Aug.2019