Datasheet

The most MRS command to Non-MRS command delay, t
MOD
, is required for the DRAM to update the features,
and is the minimum time required from an MRS command to a non-MRS command excluding DES, as shown
in the t
MOD
timing figure.
Some of the mode register setting cases, function updating takes longer than t
MOD
. The MRS commands that
do not apply t
MOD
timing to next valid command excluding DES is listed in Note 2 of t
MOD
timing figure. These
MRS command input cases have unique MR setting procedure, so refer to individual function description.
t
MOD
VALIDVALID MRS
2
DES DES DES DES DES VALID VALID VALID
VALIDVALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
CK#
ADDR
CK
CMD
CKE
NOTE 1. This timing diagram shows C/A Parity Latency mode is “Disable” case.
NOTE 2. List of MRS commands exception that do not apply to t
MOD
- DLL Enable, DLL Reset
- V
REFDQ
training Value, internal V
REF
Monitor, V
REFDQ
Training mode and V
REFDQ
training Range
- Gear down mode
- Per DRAM addressability mode
- CA Parity mode
DON'T CARETIME BREAK
T1 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2T0 Tb3
Old Settings Updating Settings
Settings
New Settings
Figure 7. t
MOD
timing
CK#
ODT
CK
RTT
DODTLoff + 1
NOTE 1. This timing diagram shows C/A Parity Latency mode is “Disable” case.
NOTE 2. When an MRS command mentioned in this note affects R
TT_NOM
turn on timings, R
TT_NOM
turn off timings and R
TT_NOM
value,
this means the MR register value changes. The ODT signal should set to be low for at least DODTLoff +1 clock before their affecting
MRS command is issued and remain low until t
MOD
expires. The following MR registers affects R
TT_NOM
turn on timings, R
TT_NOM
turn off
timings and R
TT_NOM
value and it requires ODT to be low when an MRS command change the MR register value. If there are no change
the MR register value that correspond to commands mentioned in this note, then ODT signal is not require to be low.
- DLL control for precharge power down
- Additive latency and CAS read latency
- DLL enable and disable
- CAS write latency
- CA Parity mode
- Gear down mode
- R
TT_NOM
t
MOD
t
ADC_min
t
ADC_max
t
ADC_min
t
ADC_max
CMD
R
TT_NOM
MRS
R
TT_NOM
Figure 8. ODT Status at MRS affecting ODT turn-on/off timing
The mode register contents can be changed using the same command and timing requirements during normal
operation as long as the device is in idle state, i.e., all banks are in the precharged state with t
RP
satisfied, all
data bursts are completed and CKE is high prior to writing into the mode register. If R
TT_NOM
function is intended
to change (enable to disable and vice versa) or already enabled in DRAM MR, ODT signal must be registered
Low ensuring R
TT_NOM
is in an off state prior to MRS command affecting R
TT_NOM
turn-on and off timing. The
ODT signal may be registered high after t
MOD
has expired. ODT signal is a don’t care during MRS command if
DRAM R
TT_NOM
function is disabled in the mode register prior and after an MRS command.
AS4C256M16D4
Confidential
- 14 of 201 -
Rev.1.0 Aug.2019