Datasheet

Connectivity Test ( CT ) Mode Input Levels
Following input parameters will be applied for DDR4 SDRAM Input Signal during Connectivity Test Mode.
Table 47. CMOS rail to rail Input Levels for TEN
Parameter
Symbol
Min.
Max.
Unit
Note
TEN AC Input High Voltage
V
IH(AC)
_TEN
0.8 x V
DD
V
DD
V
1
TEN DC Input High Voltage
V
IH(DC)
_TEN
0.7 x V
DD
V
DD
V
TEN DC Input Low Voltage
V
IL(DC)
_TEN
V
SS
0.3 x V
DD
V
TEN AC Input Low Voltage
V
IL(AC)
_TEN
V
SS
0.2 x V
DD
V
2
TEN Input signal Falling time
T
F_input
_TEN
-
10
ns
TEN Input signal Rising time
T
R_input
_TEN
-
10
ns
Note 1. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.
Note 2. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings.
0.8xV
DD
TR_input_TEN
0.7xV
DD
0.3xV
DD
0.2xV
DD
TF_input_TEN
Figure 155. TEN Input Slew Rate Definition
Table 48. Single-Ended AC and DC Input levels for CS#, BA0-1, BG0, A0-A9, A10/AP, A12/BC#, A13,
WE#/A14, CAS#/A15, RAS#/A16, CKE, ACT#, ODT, CK, CK# and PAR
Parameter
Symbol
Min.
Max.
Unit
Note
CTipA AC Input High Voltage
V
IH(AC)
_CTipA
V
REFCA
+ 0.2
-
V
1
CTipA DC Input High Voltage
V
IH(DC)
_CTipA
V
REFCA
+ 0.15
V
DD
V
CTipA DC Input Low Voltage
V
IL(DC)
_CTipA
V
SS
V
REFCA
- 0.15
V
CTipA AC Input Low Voltage
V
IL(AC)
_CTipA
-
V
REFCA
- 0.2
V
1
CTipA Input signal Falling time
T
F_input
_CTipA
-
5
ns
CTipA Input signal Rising time
T
R_input
_CTipA
-
5
ns
Note 1. See “Overshoot and Undershoot Specifications”.
TF_input_CTipA
V
IH(AC)_CTipA min
TR_input_CTipA
V
IH(DC)_CTipA min
V
IL(DC)_CTipA max
V
IL(AC)_CTipA max
V
REFCA
Figure 156. CS# and Input A Slew Rate Definition
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019