Datasheet

Input level and Timing Requirement
During CT Mode, input levels are defined below.
TEN pin: CMOS rail-to-rail with DC high and low at 80% and 20% of V
DD
CS#: Pseudo differential signal referring to V
REFCA
Test Input pin A: Pseudo differential signal referring to V
REFCA
Test Input pin B: Pseudo differential signal referring to internal V
REF
0.5 x V
DD
RESET#: CMOS DC high above 70 % V
DD
ALERT#: Terminated to V
DD
. Swing level is TBD
Prior to the assertion of the TEN pin, all voltage supplies must be valid and stable.
Upon the assertion of the TEN pin, the CK and CK# signals will be ignored and the DDR4 memory device
enter into the CT mode after t
CT_Enable.
In the CT mode, no refresh activities in the memory arrays, initiated
either externally (i.e., auto-refresh) or internally (i.e., self-refresh), will be maintained.
The TEN pin may be asserted after the DRAM has completed power-on; once the DRAM is initialized and
V
REFDQ
is calibrated, CT Mode may no longer be used.
The TEN pin may be de-asserted at any time in the CT mode. Upon exiting the CT mode, the states of the
DDR4 memory device are unknown and the integrity of the original content of the memory array is not
guaranteed and therefore the reset initialization sequence is required.
All output signals at the test output pins will be stable within t
CT_Valid
after the test inputs have been applied to
the test input pins with TEN input and CS# input maintained High and Low respectively.
CK#
CK
CKE
t
CT_IS
CT Inputs
TEN
VALID Input
CS#
RESET#
VALID Input
VALID InputVALID Input
t
CTCKE_Valid>=10ns
t
CT_Enable
VALID InputVALID Input
VALID Input VALID Input
t
CT_IS>=0ns
t
CT_Valid
CT Outputs
Figure 154. Timing Diagram for Connectivity Test(CT) Mode
Table 46. AC parameters for Connectivity Test (CT) Mode
Symbol
Min.
Max.
Unit
t
CT_IS
0
-
ns
t
CT_Enable
200
-
ns
t
CT_Valid
-
200
ns
AS4C256M16D4
Confidential
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Rev.1.0 Aug.2019