Datasheet

Connectivity Test Mode
Introduction
The DDR4 memory device supports a connectivity test (CT) mode, which is designed to greatly speed up
testing of electrical continuity of pin interconnection on the PC boards between the DDR4 memory devices
and the memory controller on the SoC. Designed to work seamlessly with any boundary scan devices, the CT
mode is required for all x16 width devices independant of density.
Contrary to other conventional shift register based test mode, where test patterns are shifted in and out of the
memory devices serially in each clock, DDR4’s CT mode allows test patterns to be entered in parallel into the
test input pins and the test results extracted in parallel from the test output pins of the DDR4 memory device
at the same time, significantly enhancing the speed of the connectivity check. RESET# is registered to High
and V
REFCA
must be stable prior to entering CT mode. Once put in the CT mode, the DDR4 memory device
effectively appears as an asynchronous device to the external controlling agent; after the input test pattern is
applied, the connectivity check test results are available for extraction in parallel at the test output pins after a
fixed propagation delay. During CT mode, any ODT is turned off.
A reset of the DDR4 memory device is required after exiting the CT mode.
Pin Mapping
Only digital pins can be tested via the CT mode. For the purpose of connectivity check, all pins that are used
for the digital logic in the DDR4 memory device are classified as one of the following types:
1) Test Enable (TEN) pin: when asserted high, this pin causes the DDR4 memory device to enter the CT
mode. In this mode, the normal memory function inside the DDR4 memory device is bypassed and the IO
pins appear as a set of test input and output pins to the external controlling agent; additionally, the DRAM
will set the internal V
REFDQ
to V
DDQ
x 0.5 during CT mode (this is the only time the DRAM takes direct control
over setting the internal V
REFDQ
). The TEN pin is dedicated to the connectivity check function and will not be
used during normal memory operation.
2) Chip Select (CS#) pin: when asserted low, this pin enables the test output pins in the DDR4 memory device.
When de-asserted, the output pins in the DDR4 memory device will be tri-stated. The CS# pin in the DDR4
memory device serves as the CS# pin when in CT mode.
3) Test Input: a group of pins that are used during normal DDR4 DRAM operation are designated test input
pins. These pins are used to enter the test pattern in CT mode.
4) Test Output: a group of pins that are used during normal DDR4 DRAM operation are designated test output
pins. These pins are used for extraction of the connectivity test results in CT mode.
5) RESET#: Fixed high level is required during CT mode same as normal function.
Table 44. Pin Classification of DDR4 Memory Device in Connectivity Test (CT) Mode
CT Mode Pins
Pin Names during Normal Memory Operation
Test Enable
TEN
Chip Select
CS#
Test Input
A
BA0-1, BG0, A0-A9, A10/AP, A12/BC#, A13, WE#/A14, CAS#/A15, RAS#/A16, CKE, ACT#, ODT, CK, CK#, PAR
B
LDM#/LDBI#, UDM#/UDBI#
C
ALERT#
D
RESET#
Test Output
DQ0 – DQ15, LDQS, LDQS#, UDQS, UDQS#
Table 45. TEN Pin Weak Pull Down Strength Range
Symbol
Description
Min.
Max.
Unit
TEN
TEN pin should be internally pulled low to prevent DDR4 SDRAM from
conducting Connectivity Test mode in case that TEN is not used.
0.05
10
μA
Note 1. The host controller should use good enough strength when activating connectivity test mode to avoid current fighting at TEN
signal and inability of connectivity test mode.
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